When discussing PCB Flying Probe Test, it’s important to understand what Flying Probe Test entails. This method is used to assess the electrical function of PCBs, specifically to check for open and short circuits. A flight tester is a system designed for testing PCBs during the production process. Instead of the traditional bed-of-nails interfaces found in in-circuit test machines, flying probe testing utilizes four to eight independently controlled probes that move to the component under test. The unit under test (UUT) is transported into the testing machine by means of a belt or other UUT conveying system. Once fixed in place, the probes of the tester make contact with test pads and vias to assess the individual components of the UUT. Test probes are connected to drivers (signal generators, power supplies, etc.) and sensors (digital multimeters, frequency counters, etc.) through a multiplexing system to test components on the UUT. While one element is being tested, others on the UUT are electrically shielded by the prober to prevent reading interference.
Here are the structured steps for creating a flying probe test program:
Method One:
1. Import the layer file, check, arrange, align, etc., and then rename the two outer layers to fronrear. Rename the inner layer to ily02, ily03, ily04neg (if it is a negative film), rear, rearmneg.
2. Add three layers, copy the two solder mask layers and the drilling layer respectively to the added three layers, and change the names to fronmneg, rearmneg, mehole. Those with blind buried holes can be named met01-02.,met02- 05, met05-06, etc.
3. Change the two layers of the copied fronmneg and rearmneg to the round of 8mil. We call fronmneg the front layer test point and rearmneg the back test point.
4. Delete the NPTH hole, find the via hole according to the circuit, and define the unmeasured hole.
5. Change fron and mehole as the reference layer, change the fronmneg layer to on, and check to see if the test points are all at the window opening of the front layer circuit. Test points in holes larger than 100 mil should be moved to the solder ring for testing. The test points at the BGA that are too dense should be misplaced. Some redundant intermediate test points can be appropriately deleted. The back layer operates the same.
6. Copy the sorted test point fronmneg to the fron layer, and copy the rearmneg to the rear layer.
7. Activate all layers and move to 10,10mm.
8. The output gerber files are named fron, ily02, ily03, ily04neg, ilyo5neg, rear, fronmneg, rearmneg, mehole, met01-02, met02-09, met09-met10 layers. Next, use Ediapv software to continue the process.
A. Using this method to create test files often results in many test points, and the intermediate points cannot be automatically deleted.
B. The testing of holes may not be well understood, as there are instances of generated connectivity (open circuit) test points in ediapv with no test points for individual holes. Additionally, there may be inconsistencies in the test points generated for holes.
C. If there is no window for the REAR surface solder mask, the name of the REAR layer can be changed to avoid any confusion.
E. If there is a MEHOLE with only one window on both sides, but there are test points on both sides, the make test programs button should be pressed again. The cursor can be placed above the MEHOLE layer to delete measuring points on holes without windows for solder mask.
F. It is crucial to ensure the names of the layers are accurate to avoid issues later on.
