There are many ways to solve EMI problems. Modern EMI suppression methods include: using EMI suppression coatings, selecting appropriate EMI suppression parts, and EMI simulation design. Starting from the most basic PCB printed circuit board layout, let’s discuss the role of PCB layer stacking in controlling EMI radiation and explore design techniques.
**Power Bus**
Properly placing a capacitor with suitable capacitance near the power supply pin of the IC can improve the IC’s output voltage stability. However, the solution does not end there. Due to the limited frequency response of the capacitor, it cannot provide the harmonic power needed to maintain a clean IC output across the full frequency range. Additionally, transient voltages on the power bus can create voltage drops across the inductance of the decoupling path, making these transient voltages a significant source of common-mode EMI interference. So, how can we address these issues?
For the IC on our circuit board, the power layer surrounding the IC can act as an effective high-frequency capacitor, capturing some of the energy that the discrete capacitor cannot handle and thus supporting a clean output. Furthermore, a well-designed power layer should have minimal inductance, which reduces the transient signals synthesized by the inductance and, consequently, common-mode EMI.
Of course, the connection between the power layer and the IC power pin should be as short as possible. As digital signal edges become faster, it is ideal to connect it directly to the pad where the IC power pin is located. This topic warrants a more detailed discussion.
To control common-mode EMI, the power plane must assist with decoupling and possess sufficiently low inductance. This power plane must be a well-designed pair of power planes. One might wonder what constitutes “good.” The answer depends on factors such as the power supply layering, the materials between the layers, and the operating frequency (which is related to the rise time of the IC). Typically, with a layer spacing of 6 mils and using FR4 material between layers, the equivalent capacitance of the power layer per square inch is approximately 75 pF. Clearly, reducing the layer spacing increases the capacitance.
1. There are not many devices with a rise time of 100 to 300 ps, but given the current IC development speed, devices within this rise time range will likely occupy a significant proportion of the market. For circuits with a rise time of 100 to 300 ps, a 3-mil layer spacing is becoming unsuitable for most applications. At that point, it will be necessary to use layering technology with a spacing of less than 1 mil and replace FR4 dielectric materials with those possessing a higher dielectric constant. Presently, ceramics and ceramic plastics can meet the design requirements for circuits with a 100 to 300 ps rise time.
2. Although new materials and methods may emerge in the future, for today’s common 1 to 3 ns rise time circuits, 3 to 6 mil layer spacing and FR4 dielectric materials are usually sufficient to manage high-end harmonics and minimize transient signals. This means that common mode EMI can be reduced to a very low level. The PCB printed circuit board stacking design examples in this article will assume a layer spacing of 3 to 6 mils.
3. **Electromagnetic Shielding**
From the perspective of signal traces, an effective layering strategy is to place all signal traces on one or more layers adjacent to the power or ground layers. For the power supply, an optimal layering strategy involves placing the power layer next to the ground layer with the smallest possible distance between them. This approach is what we refer to as the “layering” strategy.
4. **PCB Printed Circuit Board Stacking**
What stacking strategy aids in shielding and suppressing EMI? The following layered stacking scheme assumes that the power supply current flows on a single layer, with either a single voltage or multiple voltages distributed across different parts of the same layer. The scenario involving multiple power layers will be discussed later.
5. **4-Layer Board**
Several potential issues arise with the 4-layer board design. Firstly, in a traditional 4-layer board with a thickness of 62 mils, even with the signal layer on the outer layer and power and ground layers on the inner layers, the distance between the power and ground layers remains too large.
6. If cost is the primary concern, consider these two traditional 4-layer board alternatives. Both solutions can enhance EMI suppression performance but are suitable only for applications with low component density and sufficient space around components (for placing the required power copper layer).
7. The first is the preferred solution: the outer layers of the PCB are ground layers, while the middle two layers serve as signal/power layers. Routing the power supply on the signal layer with wide lines reduces the path impedance for the power supply current and also lowers the impedance of the signal microstrip path. From an EMI control perspective, this is the most effective 4-layer PCB structure available.
8. The second scheme features power and ground on the outer layers and signals on the middle two layers. The improvement compared to the traditional 4-layer board is less significant, and interlayer impedance remains similar to that of the traditional 4-layer board.
9. To control trace impedance, the above stacking scheme must carefully arrange traces beneath the power and ground copper islands. Additionally, copper islands on the power supply or ground layers should be interconnected as much as possible to ensure DC and low-frequency connectivity.
**Power Bus**
Properly placing a capacitor with suitable capacitance near the power supply pin of the IC can improve the IC’s output voltage stability. However, the solution does not end there. Due to the limited frequency response of the capacitor, it cannot provide the harmonic power needed to maintain a clean IC output across the full frequency range. Additionally, transient voltages on the power bus can create voltage drops across the inductance of the decoupling path, making these transient voltages a significant source of common-mode EMI interference. So, how can we address these issues?
For the IC on our circuit board, the power layer surrounding the IC can act as an effective high-frequency capacitor, capturing some of the energy that the discrete capacitor cannot handle and thus supporting a clean output. Furthermore, a well-designed power layer should have minimal inductance, which reduces the transient signals synthesized by the inductance and, consequently, common-mode EMI.
Of course, the connection between the power layer and the IC power pin should be as short as possible. As digital signal edges become faster, it is ideal to connect it directly to the pad where the IC power pin is located. This topic warrants a more detailed discussion.
To control common-mode EMI, the power plane must assist with decoupling and possess sufficiently low inductance. This power plane must be a well-designed pair of power planes. One might wonder what constitutes “good.” The answer depends on factors such as the power supply layering, the materials between the layers, and the operating frequency (which is related to the rise time of the IC). Typically, with a layer spacing of 6 mils and using FR4 material between layers, the equivalent capacitance of the power layer per square inch is approximately 75 pF. Clearly, reducing the layer spacing increases the capacitance.
1. There are not many devices with a rise time of 100 to 300 ps, but given the current IC development speed, devices within this rise time range will likely occupy a significant proportion of the market. For circuits with a rise time of 100 to 300 ps, a 3-mil layer spacing is becoming unsuitable for most applications. At that point, it will be necessary to use layering technology with a spacing of less than 1 mil and replace FR4 dielectric materials with those possessing a higher dielectric constant. Presently, ceramics and ceramic plastics can meet the design requirements for circuits with a 100 to 300 ps rise time.
2. Although new materials and methods may emerge in the future, for today’s common 1 to 3 ns rise time circuits, 3 to 6 mil layer spacing and FR4 dielectric materials are usually sufficient to manage high-end harmonics and minimize transient signals. This means that common mode EMI can be reduced to a very low level. The PCB printed circuit board stacking design examples in this article will assume a layer spacing of 3 to 6 mils.
3. **Electromagnetic Shielding**
From the perspective of signal traces, an effective layering strategy is to place all signal traces on one or more layers adjacent to the power or ground layers. For the power supply, an optimal layering strategy involves placing the power layer next to the ground layer with the smallest possible distance between them. This approach is what we refer to as the “layering” strategy.
4. **PCB Printed Circuit Board Stacking**
What stacking strategy aids in shielding and suppressing EMI? The following layered stacking scheme assumes that the power supply current flows on a single layer, with either a single voltage or multiple voltages distributed across different parts of the same layer. The scenario involving multiple power layers will be discussed later.
5. **4-Layer Board**
Several potential issues arise with the 4-layer board design. Firstly, in a traditional 4-layer board with a thickness of 62 mils, even with the signal layer on the outer layer and power and ground layers on the inner layers, the distance between the power and ground layers remains too large.
6. If cost is the primary concern, consider these two traditional 4-layer board alternatives. Both solutions can enhance EMI suppression performance but are suitable only for applications with low component density and sufficient space around components (for placing the required power copper layer).
7. The first is the preferred solution: the outer layers of the PCB are ground layers, while the middle two layers serve as signal/power layers. Routing the power supply on the signal layer with wide lines reduces the path impedance for the power supply current and also lowers the impedance of the signal microstrip path. From an EMI control perspective, this is the most effective 4-layer PCB structure available.
8. The second scheme features power and ground on the outer layers and signals on the middle two layers. The improvement compared to the traditional 4-layer board is less significant, and interlayer impedance remains similar to that of the traditional 4-layer board.
9. To control trace impedance, the above stacking scheme must carefully arrange traces beneath the power and ground copper islands. Additionally, copper islands on the power supply or ground layers should be interconnected as much as possible to ensure DC and low-frequency connectivity.
