**1. Design Process**

The PCB design process consists of six main steps: netlist input, rule setup, component placement, routing, inspection, review, and output.

**1.1 Netlist Input**

There are two methods for entering the netlist. The first method involves using PowerLogic’s OLE PowerPCB Connection function. By selecting “Send Netlist,” the OLE function ensures the schematic and PCB diagrams remain synchronized at all times, minimizing the risk of errors.

Alternatively, the netlist can be directly imported into PowerPCB by selecting *File -> Import* and loading the netlist generated from the schematic diagram.

**1.2 Rule Setup**

If design rules were already established during the schematic design phase, there is no need to reconfigure them, as they will be automatically imported into PowerPCB along with the netlist. However, if any design rules are updated, the schematic must be synchronized to ensure consistency between the schematic and the PCB design.

In addition to basic design rules and layer definitions, other settings, such as Pad Stacks, also need to be adjusted, especially when modifying via sizes. When a new pad or via is created, be sure to include Layer 25.

**Note:**

PCB layout design rules, layer definitions, via settings, and CAM output configurations are preconfigured in the default startup file. After the netlist is input, the power and ground nets are assigned to the power layers based on the design requirements. Additionally, advanced rules are set as needed. Once all rules are configured, use the “Rules From PCB” function in PowerLogic’s OLE PowerPCB Connection to update the schematic rules, ensuring both the schematic and PCB rules are aligned.

**1.3 Component Layout**

Once the netlist is loaded, all components are initially placed at the origin of the workspace, overlapping each other. The next step is to separate and organize the components in a logical manner—this is the component layout phase. PowerPCB offers two methods for component placement: Manual Layout and Auto Layout.

**2. Manual Layout**

**2.1** Draw the board outline according to the structural dimensions of the printed circuit board.

**2.2** Distribute components around the edges of the board.

**2.3** Move and rotate each component individually, placing them inside the board’s outline and arranging them neatly according to specific design guidelines.

**3. Auto Layout**


PowerPCB provides both automatic layout and automatic local cluster layout, but for most designs, the results are not optimal and are generally not recommended.

1.3.3 Precautions

a. The primary goal in layout is to ensure a high routing efficiency and to manage the connections of flying leads carefully when connecting devices. Arrange the connected devices in close proximity.

b. Where possible, separate digital devices from analog devices.

c. Place decoupling capacitors as close as possible to the VCC pin of each device.

d. When positioning devices, consider future soldering requirements, avoiding overly dense placements.

e. Utilize the Array and Union functions provided by the software to enhance layout efficiency.

1.4 There are two primary methods for routing: manual routing and automatic routing. PowerPCB’s manual routing function is very powerful, offering automatic pushing and online design rule checking (DRC). Automatic routing is handled by the Specctra routing engine. Typically, a combination of both methods is used, with the common workflow being manual-automatic-manual.

4. Manual Routing

4.1 Before starting automatic routing, manually route critical networks such as high-frequency clocks and the main power supply. These networks often have special requirements regarding trace distance, width, spacing, shielding, etc. Additionally, certain complex packages, such as BGAs, can be difficult for the automatic router to handle, and manual routing is necessary.

4.2 After the automatic routing is complete, manual adjustments may be required to fine-tune the PCB layout.

4.3 Automatic Routing

Once manual routing is finished, hand off the remaining networks to the automatic router. To do this, select Tools → SPECCTRA to launch the Specctra router interface. Set the DO file and click Continue to begin the automatic routing process. If the routing completion rate is 100%, manual adjustments can be made. If the rate is less than 100%, it indicates issues with the layout or manual routing, which must be addressed until all connections are routed correctly.

5. Key Considerations

a. Make the power and ground traces as thick as possible.

b. Aim to connect the decoupling capacitors directly to VCC.

c. When setting up the Specctra DO file, add the “Protect all wires” command first, to prevent manually routed wires from being altered by the auto-router.

d. If using a mixed power layer, define the layer as a Split/Mixed Plane. After dividing the layers and routing, use Plane Connect in Pour Manager for copper pour.

e. Set all device pins to thermal pad mode by selecting Filter → Pins, choosing all pins, modifying their properties, and enabling the Thermal option.

f. Enable the DRC option during manual routing and use Dynamic Route.

1.5 Design Verification

The verification process checks several parameters, including Clearance, Connectivity, High Speed, and Plane. These checks can be performed by choosing Tools → Verify Design. If high-speed rules are configured, they must be checked; otherwise, this step can be skipped. If any errors are found, the layout or routing must be adjusted.

**Note:**

Some errors can be ignored, such as when a part of a connector’s outline extends outside the board frame, which may trigger a spacing error during checking. Also, each time traces or vias are modified, copper must be re-poured.

6. Design Review

PCB manufacturers conduct a review based on the “PCB checklist,” which covers design rules, layer definitions, trace widths, spacing, pad configurations, and via settings. Additionally, attention should be given to the rationality of device placement, the routing of power and ground networks, high-speed signal routing and clock network shielding, as well as the placement and connections of decoupling capacitors. If the recheck fails, the designer must modify the layout and routing. Once the design passes, both the rechecker and the designer must sign off.

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