As the complexity and density of circuit boards continue to escalate, the challenge of testing and debugging limited test points with oscilloscopes and logic analyzers has become increasingly burdensome, leading to diminished efficiency. Emerging EDA simulators and waveform viewers leverage thousands of time domains to monitor signals, significantly broadening the debugging scope. This article will delve into the powerful capabilities of board-level simulation technology and its ultimate role in reducing the circuit board design and production cycle.
Regardless of how advanced the development tools may be, both minor and major defects will inevitably arise throughout the development process, often lurking at various stages of design, implementation, and CAD. While the presence of defects is not alarming, identifying and addressing them as early as possible is crucial for effectively saving time and money. Board-level simulation tools assist PCB designers in expediting debugging efforts both before and after circuit board manufacturing.
**Board Level Simulation Technology**
The main steps involved in board-level simulation are as follows:
a. **Develop a Test Plan**
The initial step in the simulation process is to create a comprehensive test plan that fully reflects the product’s specific requirements regarding board-level simulation. This test plan can be divided into two phases for implementation: Phase 1 focuses on individual interface testing, while Phase 2 addresses the overall functional testing of the circuit board.
1. **Phase 1** requires a clear definition of the interface type and scope, ensuring complete isolation, such as between the processor and memory interface. Subsequently, create a test case to evaluate the connection performance and timing characteristics of the interface.
2. **Stage 2** involves dividing the circuit board into multiple functional blocks (each block may host one or more interfaces). Once each interface is confirmed operational in Phase 1, focus on the functionality of a single module, treating the entire circuit board as a black box. At this stage, utilize appropriate test vectors to address synthesized timing issues and specific data for the functional block.
3. **Establishment of Simulation Environment**
A comprehensive simulation environment must be established prior to simulation to support, process, and analyze various input signals while measuring output signals. The simulation environment should encompass: 1. Checkers and monitors; 2. Netlist; 3. Model; 4. Directory structure;
4. **Checkers and Monitors**
After formulating the test plan, any errors or defects are automatically logged. When input excitation signals are applied to the circuit board, ideal output results are expected, but simulation outcomes can vary. Time-consuming analysis of the output results can be mitigated by writing a comparison script. Additionally, employing flags to indicate fault conditions during simulation achieves similar efficiency.
5. When simulating timing and data integrity issues, the task that identifies defects is referred to as a monitor, while the script used for simulating functional characteristics and comparing final results is known as a checker. Although this method may initially require time, it significantly reduces waveform search and result analysis during the actual testing phase.
6. **Netlist**
Common schematic input tools offer functionality for generating Verilog/VHDL netlists. These netlists encompass all components and their network connections, with component and port names represented by symbols.
7. **Model**
The simulation necessitates an HDL model for each component. Standard chip Verilog/VHDL model libraries can be sourced from Synopsys or other suppliers. These models function identically to actual components, with flexible timing adjustments to meet current requirements. While component and port names in the netlist match those declared in the schematic, names in the actual model may differ. To connect ports in the netlist to the model correctly, a package file is needed, establishing the port mapping relationship for components with differing names. For instance, if a component pin is labeled OE_ but the model port is oe_n, a package file is essential for connecting the netlist symbol pin to the model port.
8. **Directory Structure**
Typically, PCB designers must create a proper directory structure to track the input/output signals throughout the simulation process. These directories help distinguish various types of environment files, including: cs, local development models, monitors/inspectors, scripts, board-level netlists, log files, dump files, and more. An effective directory structure aids in managing and tracking all environment and code files.
9. Utilizing the framer/deframer as the simulated functional block (assuming normal operation of the PCI bus controller, system controller, and arbiter, with testing focused solely on the framer/deframer), input the excitation signal from the PCI side and verify the output on the T1/E1 digital line side, then reverse the process.
10. Typical test scenarios include: 1. Frames with varied data content; 2. Frame delays; 3. Super frames or extended super frames with different parameter settings; 4. Frames exhibiting CRC errors, among others.
11. Other functional blocks can be simulated similarly to check simulation results. Possible defects during this testing phase may include: 1. Duplicate network names in different function blocks, often causing short circuits; 2. System integration issues, such as signals routing incorrectly between interfaces; 3. An interface’s data format being unsupported by others. This stage is often referred to as the data channel simulation of the circuit board.
12. **Simulation Skills**
Below are some board-level simulation tips: 1. For programmable PCB components, leverage back-labeling files containing predictable input and output signal timing information; 2. Verify all power supply network descriptions in the netlist, addressing any omissions immediately; 3. The final netlist will not be directly tied to the circuit board; such components require attention.
13. Although functional simulation offers numerous advantages, it has limitations that prevent simulation results from fully mirroring actual PCB behavior. These limitations include: 1. The absence of distinct power network identifications; HDL allows power networks to be declared, but not specific values like 5V or 3.3V. The current HDL version does not support this feature. 2. HDL cannot simulate analog interfaces. 3. This simulation approach may miss drive capability issues. 4. Memory tests necessitate large dump files and extended execution times.
