2. Single-sided pads should be clearly marked if they are drilled.

5. Use filler blocks to draw pads.

Drawing pads with filler blocks can pass DRC inspections during circuit design, but they pose challenges for processing. Therefore, solder mask data cannot be directly generated from these pads. When the solder resist is applied, the filler block area will be covered, making it difficult to solder the component.

6. The electrical ground layer is also a flower pad and a connection.

Since the power supply is designed as a flower pad, the ground layer will appear inverted compared to the actual printed board, with all connections represented as isolated lines. Designers must be aware of this. Additionally, when creating multiple sets of power supplies or ground isolation lines, care must be taken to avoid leaving gaps, which could short-circuit the power supplies and block the connection areas.

7. The processing level is not clearly defined.

1. The single-sided board is designed on the TOP layer. If the front and back are not specified, it may complicate the soldering of components during manufacturing.

2. For instance, a four-layer board designed with TOP, mid1, mid2, and bottom layers must be processed in that specific order; otherwise, additional clarification is required.

8. There are too many filler blocks in the design, or the filler blocks are filled with very thin lines.

1. The Gerber data may be lost or incomplete.

2. If the filler blocks are drawn individually with lines when processing the light drawing data, it significantly increases the data volume, complicating data processing.

9. The surface mount device pad is too short.

This affects continuity testing. For densely packed surface mount devices, the spacing between pins is minimal, leading to very thin pads. Test pins must be staggered vertically or horizontally. If pads are designed too short, it won’t affect installation but will hinder proper staggering of test pins.

10. The spacing of large-area grids is too small.

The gaps between the lines that form a large area of grid lines should be at least 0.3mm. During the PCB manufacturing process, small gaps can lead to broken films, resulting in wire breakage.

11. The distance between large area copper foil and the outer frame is too close.

This distance should be at least 0.2mm. When milling the copper foil shape, insufficient distance can cause warping and may lead to the solder resist peeling off.

12. The design of the outline frame is not clear.

Some customers design contour lines in Keeplayer, Boardlayer, Topoverlayer, etc., but if these lines do not overlap, it creates confusion for PCB manufacturers regarding which contour line takes precedence.

13. PCB graphic design is uneven.

During pattern plating, uneven plating layers can negatively affect quality.

14. When the copper area is too large, grid lines should be used to prevent blistering during SMT.

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