1. The gigabit serial I/O technology exhibits extremely outstanding performance, but this performance requires certain conditions to be met, namely excellent signal integrity.
2. For instance, a supplier reported that their initial attempts to use a high-speed, gigabit serial design for a specific application resulted in a 90% failure rate.
3. To enhance the success rate, simulations and the adoption of more complex new bypass circuits may be necessary.
4. The GTP performance of Spartan-6 FPGA is contingent upon the signal integrity of the PCB.
5. The following factors need to be considered in the PCB design process: the board’s laminated structure, component layout, and signal routing.
1. Power Supply and Stackup
2. For the GTP transceiver of the Spartan-6 FPGA, the stack can be divided into two groups: the power distribution layer and the signal routing layer.
3. The power layer is used to connect the MGTACC, MGTAVCCPLL, MGTAVTTTX, and MGTAVTTRX power pins of the GTP.
4. In the stack, the ground plane layer provides a return path for the signal transmission.
5. Additionally, because there is a shielded plane between the two signal layers, it is unnecessary to consider the routing issues of adjacent layers, allowing for more signal paths.
6. The power plane for the GTP should be closely adjacent to the ground plane to enhance the coupling effect.
7. The ground plane can shield the GTP’s power plane from noise interference caused by signals from the upper or lower layers.
8. From another perspective, when power supply noise occurs in the high-frequency range, it becomes increasingly difficult to find a capacitor that covers this frequency range and effectively filters it.
9. As capacitance value decreases, related stray inductance and package resistance remain unchanged, so frequency response does not vary significantly.
10. To achieve better power distribution at high speeds, it is essential to use power and ground layers to construct effective capacitors.
11. To meet our objectives more effectively, it is generally necessary to use adjacent power and ground planes.
12. The connection between the GTP’s power supply pins and the power distribution network is crucial for GTP performance.
13. The PDN and FPGA require low-impedance and low-noise connections.
14. The FPGA’s GTP power supply can tolerate a maximum noise level of 10mVpp.
15. In the range of 10KHz to 80MHz, a small power plane can be used. This small plane should not cover the SelectIO interface area.
16. PCB Design Capacitor Placement
17. In addition to considering the value of the bypass capacitor, the placement of the capacitor is also crucial.
18. The general rule is that larger capacitance values have less stringent placement requirements.
19. If the capacitor value is small, the capacitor should be placed as close as possible to the power and ground pins.
20. One method is to remove traces and vias from unused general-purpose IOs to make room for the bypass capacitor.
21. Consider the placement of the GTP power segmentation area and the GTP filter capacitor location.
22. Signal Routing
23. GTP signal traces and SelectIO signal traces should not be on adjacent layers, and their return paths should be kept separate, including vias.
24. It is important to maintain a certain distance between differential line pairs and between differential lines and other lines.
25. The general rule is that the distance between adjacent line pairs must be at least 5 times the distance between the two lines in a pair.
26. Gigabit signal differential lines should avoid changing layers whenever possible.
27. If cross-layer transmission is necessary, special care is required.
28. Firstly, a complete return path must be provided. Thus, the reference layers of layers A and B must be coupled.
29. The ideal situation is when both reference layers are planes. In this case, place another via near the transfer layer via to connect the two reference layers.
30. If the reference planes differ (one being a ground plane and the other a power plane), place a 0.01μF capacitor as close as possible to the via connecting the two reference planes to reduce the impedance of the return path.
31. Many issues may arise during PCB design, but careful attention to every detail will result in a well-designed PCB schematic.
2. For instance, a supplier reported that their initial attempts to use a high-speed, gigabit serial design for a specific application resulted in a 90% failure rate.
3. To enhance the success rate, simulations and the adoption of more complex new bypass circuits may be necessary.
4. The GTP performance of Spartan-6 FPGA is contingent upon the signal integrity of the PCB.
5. The following factors need to be considered in the PCB design process: the board’s laminated structure, component layout, and signal routing.
1. Power Supply and Stackup
2. For the GTP transceiver of the Spartan-6 FPGA, the stack can be divided into two groups: the power distribution layer and the signal routing layer.
3. The power layer is used to connect the MGTACC, MGTAVCCPLL, MGTAVTTTX, and MGTAVTTRX power pins of the GTP.
4. In the stack, the ground plane layer provides a return path for the signal transmission.
5. Additionally, because there is a shielded plane between the two signal layers, it is unnecessary to consider the routing issues of adjacent layers, allowing for more signal paths.
6. The power plane for the GTP should be closely adjacent to the ground plane to enhance the coupling effect.
7. The ground plane can shield the GTP’s power plane from noise interference caused by signals from the upper or lower layers.
8. From another perspective, when power supply noise occurs in the high-frequency range, it becomes increasingly difficult to find a capacitor that covers this frequency range and effectively filters it.
9. As capacitance value decreases, related stray inductance and package resistance remain unchanged, so frequency response does not vary significantly.
10. To achieve better power distribution at high speeds, it is essential to use power and ground layers to construct effective capacitors.
11. To meet our objectives more effectively, it is generally necessary to use adjacent power and ground planes.
12. The connection between the GTP’s power supply pins and the power distribution network is crucial for GTP performance.
13. The PDN and FPGA require low-impedance and low-noise connections.
14. The FPGA’s GTP power supply can tolerate a maximum noise level of 10mVpp.
15. In the range of 10KHz to 80MHz, a small power plane can be used. This small plane should not cover the SelectIO interface area.
16. PCB Design Capacitor Placement
17. In addition to considering the value of the bypass capacitor, the placement of the capacitor is also crucial.
18. The general rule is that larger capacitance values have less stringent placement requirements.
19. If the capacitor value is small, the capacitor should be placed as close as possible to the power and ground pins.
20. One method is to remove traces and vias from unused general-purpose IOs to make room for the bypass capacitor.
21. Consider the placement of the GTP power segmentation area and the GTP filter capacitor location.
22. Signal Routing
23. GTP signal traces and SelectIO signal traces should not be on adjacent layers, and their return paths should be kept separate, including vias.
24. It is important to maintain a certain distance between differential line pairs and between differential lines and other lines.
25. The general rule is that the distance between adjacent line pairs must be at least 5 times the distance between the two lines in a pair.
26. Gigabit signal differential lines should avoid changing layers whenever possible.
27. If cross-layer transmission is necessary, special care is required.
28. Firstly, a complete return path must be provided. Thus, the reference layers of layers A and B must be coupled.
29. The ideal situation is when both reference layers are planes. In this case, place another via near the transfer layer via to connect the two reference layers.
30. If the reference planes differ (one being a ground plane and the other a power plane), place a 0.01μF capacitor as close as possible to the via connecting the two reference planes to reduce the impedance of the return path.
31. Many issues may arise during PCB design, but careful attention to every detail will result in a well-designed PCB schematic.
