In order to enhance the testing speed of the PCB board testing machine, streamline the circuit board design, boost the system’s reconfigurability, and improve the ease of testing algorithm transplantation, a hardware control system design scheme for the PCB board testing machine based on FPGA is proposed. The design entails the utilization of the field programmable gate array (FPGA) EP1K50 from Altera Corporation, with the hardware design and debugging of the control system being carried out using EDA design tools such as Synplify, Modelsim, Quartus II, and the Verilog hardware description language. This approach resolves issues that are challenging to address using conventional circuits.
The fundamental testing principle of the PCB board light test machine adheres to Ohm’s law. The testing methodology involves applying a specific test voltage between the designated points, utilizing a decoding circuit to select the two points on the PCB board to be tested, and determining the corresponding resistance value between these points. Through the voltage comparison circuit, the resistance or continuity between the designated points is tested. This process is repeated multiple times to evaluate the entire circuit board. Given the substantial number of points to be tested, typically exceeding 2048 points in general testing machines, the test control circuit entails increased complexity. The method of point testing and switching directly impacts the testing speed of the machine. This paper delves into the hardware control system design based on FPGA.
Hardware Control System
The test process involves controlling the test circuit to activate different test switches under the direction of the host computer. The test machine system consists of the upper computer PC104, the test control logic (implemented by FPGA), and the high-voltage test circuit. The upper computer handles human-computer interaction, test algorithm, test data processing, and control output. The FPGA controls the high-voltage test circuit to conduct the PCB board test process. This system utilizes a PC104 as the upper computer and FPGA as the control for the test through the PC104 bus.
Interface Circuit between FPGA and PC104
The PC104 bus is an industrial control bus specifically defined for embedded control, with signal definitions similar to the ISA bus. The PC104 bus has 4 types of bus cycles: 8-bit bus cycle, 16-bit bus cycle, DMA bus cycle, and refresh bus cycle. The 16-bit I/O bus cycle consists of 3 clock cycles, while the 8-bit I/O bus cycle consists of 6 clock cycles. To enhance communication speed, the ISA bus adopts a 16-bit communication mode. To fully utilize PC104 resources, the FPGA is configured online after expanding the system bus of PC104. During normal operation, it communicates with the FPGA through the PC104 bus.
Interface between FPGA and Serial A/D and D/A Devices
To meet tester system design requirements, a self-check on test voltage and two-channel reference voltage is needed, requiring at least three A/D conversion channels. The reference voltages for the two comparison circuits are output by the D/A devices, necessitating two D/A channels. Serial A/D and D/A devices were chosen to reduce control signal line numbers. The selected A/D device is TLC2543, and the D/A device is TLV5618. TLV5618 is a dual 12-bit voltage output DAC with a buffered reference input from TI, digitally controlled via a CMOS-compatible 3-wire serial bus. TLV5618 undergoes a single I/O cycle lasting 16 clock cycles, writing the command word to the on-chip register and performing D/A conversion afterwards. TLC2543 is a 12-bit A/D converter with serial control and 11 inputs from TI, featuring high speed, precision, and low noise. The functional process of TLC2543 is split into an I/O cycle and conversion cycle. The I/O cycle duration is determined by the external clock SCLK, performing two operations simultaneously: inputting 8-bit data in MSB mode on the rising edge of SCLK and outputting the conversion result in MSB mode on the falling edge of SCLK. Both devices use SPI interfaces, connect to the same SPI bus, and operate on different devices using distinct chip select signals.
FPGA Programming Framework
The on-chip FPGA program is crucial for the entire test system’s correct operation. Adhering to the top-down FPGA design principle, the system is divided into 5 independent modules: communication module (ISA), test module (TEST), AD/DA module, decoding module (DECODER), and RAM control module (RAMCTL). The ISA module is responsible for system communication and control, completing communication with the host computer, interpreting command words, and generating control signals. The system activates the ADDA module to output reference voltage based on parameters transmitted by the host computer and launches the test module to conduct test procedures. The RAM control module facilitates data sharing between the ISA and test modules by reading and writing to RAM. The test module follows a standard test procedure and saves the test results in RAM. The decoding module maps switch numbers to actual circuits, enabling the usage of test switch information output by the upper-level module. The AD/DA module designs the SPI bus interface to operate A/D and D/A devices, encapsulating D/A operations and employing 3 nested finite state machines to complete module logic functions. Each system module is written in Verilog hardware description language, using Modelsim for function simulation and QuartusII for post-system simulation, synthesis, and wiring. Altera’s IP core is utilized to optimize program modules, and the top-level design is achieved through a block diagram input method for representing data flow intuitively. The hardware control system, based on FPGA, enhances PCB board testing machine speed and simplifies circuit design, showcasing potential for software and hardware optimization and upgrades.
The fundamental testing principle of the PCB board light test machine adheres to Ohm’s law. The testing methodology involves applying a specific test voltage between the designated points, utilizing a decoding circuit to select the two points on the PCB board to be tested, and determining the corresponding resistance value between these points. Through the voltage comparison circuit, the resistance or continuity between the designated points is tested. This process is repeated multiple times to evaluate the entire circuit board. Given the substantial number of points to be tested, typically exceeding 2048 points in general testing machines, the test control circuit entails increased complexity. The method of point testing and switching directly impacts the testing speed of the machine. This paper delves into the hardware control system design based on FPGA.
Hardware Control System
The test process involves controlling the test circuit to activate different test switches under the direction of the host computer. The test machine system consists of the upper computer PC104, the test control logic (implemented by FPGA), and the high-voltage test circuit. The upper computer handles human-computer interaction, test algorithm, test data processing, and control output. The FPGA controls the high-voltage test circuit to conduct the PCB board test process. This system utilizes a PC104 as the upper computer and FPGA as the control for the test through the PC104 bus.
Interface Circuit between FPGA and PC104
The PC104 bus is an industrial control bus specifically defined for embedded control, with signal definitions similar to the ISA bus. The PC104 bus has 4 types of bus cycles: 8-bit bus cycle, 16-bit bus cycle, DMA bus cycle, and refresh bus cycle. The 16-bit I/O bus cycle consists of 3 clock cycles, while the 8-bit I/O bus cycle consists of 6 clock cycles. To enhance communication speed, the ISA bus adopts a 16-bit communication mode. To fully utilize PC104 resources, the FPGA is configured online after expanding the system bus of PC104. During normal operation, it communicates with the FPGA through the PC104 bus.
Interface between FPGA and Serial A/D and D/A Devices
To meet tester system design requirements, a self-check on test voltage and two-channel reference voltage is needed, requiring at least three A/D conversion channels. The reference voltages for the two comparison circuits are output by the D/A devices, necessitating two D/A channels. Serial A/D and D/A devices were chosen to reduce control signal line numbers. The selected A/D device is TLC2543, and the D/A device is TLV5618. TLV5618 is a dual 12-bit voltage output DAC with a buffered reference input from TI, digitally controlled via a CMOS-compatible 3-wire serial bus. TLV5618 undergoes a single I/O cycle lasting 16 clock cycles, writing the command word to the on-chip register and performing D/A conversion afterwards. TLC2543 is a 12-bit A/D converter with serial control and 11 inputs from TI, featuring high speed, precision, and low noise. The functional process of TLC2543 is split into an I/O cycle and conversion cycle. The I/O cycle duration is determined by the external clock SCLK, performing two operations simultaneously: inputting 8-bit data in MSB mode on the rising edge of SCLK and outputting the conversion result in MSB mode on the falling edge of SCLK. Both devices use SPI interfaces, connect to the same SPI bus, and operate on different devices using distinct chip select signals.
FPGA Programming Framework
The on-chip FPGA program is crucial for the entire test system’s correct operation. Adhering to the top-down FPGA design principle, the system is divided into 5 independent modules: communication module (ISA), test module (TEST), AD/DA module, decoding module (DECODER), and RAM control module (RAMCTL). The ISA module is responsible for system communication and control, completing communication with the host computer, interpreting command words, and generating control signals. The system activates the ADDA module to output reference voltage based on parameters transmitted by the host computer and launches the test module to conduct test procedures. The RAM control module facilitates data sharing between the ISA and test modules by reading and writing to RAM. The test module follows a standard test procedure and saves the test results in RAM. The decoding module maps switch numbers to actual circuits, enabling the usage of test switch information output by the upper-level module. The AD/DA module designs the SPI bus interface to operate A/D and D/A devices, encapsulating D/A operations and employing 3 nested finite state machines to complete module logic functions. Each system module is written in Verilog hardware description language, using Modelsim for function simulation and QuartusII for post-system simulation, synthesis, and wiring. Altera’s IP core is utilized to optimize program modules, and the top-level design is achieved through a block diagram input method for representing data flow intuitively. The hardware control system, based on FPGA, enhances PCB board testing machine speed and simplifies circuit design, showcasing potential for software and hardware optimization and upgrades.
