1. Basic Concept of Vias
Through-holes are integral to multilayer PCBs, with drilling costs typically comprising 30% to 40% of manufacturing expenses. Essentially, each hole in a PCB serves as a via. Functionally, vias fall into two categories: one facilitates electrical connections between layers, while the other secures or positions components. Technologically, these vias are generally classified into three types: blind vias, buried vias, and through-holes.
2. Blind holes are situated on the top and bottom PCB surfaces, penetrating to a specified depth to link surface and internal circuitry. Buried vias connect inner layers without extending to the board surface. Both types are prepared pre-lamination through hole formation, often overlapping multiple inner layers. Through-holes traverse the entire board, serving internal connections or component mounting, favored for their technical feasibility and cost efficiency.
3. By design, a via comprises a central drill hole and surrounding pad area, dictating its size. In high-speed, high-density PCB design, smaller vias are preferred to maximize board wiring space and minimize parasitic capacitance, critical for high-speed circuits. However, reducing via size escalates costs and is constrained by drilling and plating capabilities: smaller holes increase drilling time and risk center deviation, while holes deeper than 6 times their diameter pose uniform copper plating challenges.
4. With advancements in laser drilling, hole sizes continue to shrink, with diameters ≤ 6 mils termed microvias. Integral to HDI designs, microvias punched directly on pads enhance circuit performance and conserve wiring space. Vias on transmission lines act as impedance-disrupting breakpoints, inducing signal reflections. Typically, via impedance is about 12% lower than transmission lines, causing a minimal reflection coefficient (e.g., (44-50)/(44+50)=0.06). Concerns center on parasitic capacitance and inductance effects rather than significant reflection issues.
2. Parasitic Capacitance and Inductance of Vias
There are parasitic stray capacitance and inductance associated with vias. The capacitance mainly arises within the via itself. If we know the diameter of the solder mask opening around the via (D2), the diameter of the via pad (D1), the PCB thickness (T), and the dielectric constant of the PCB substrate (ε), then the parasitic capacitance (C) of the via can be approximated as:
[ C = 1.41 cdot frac{epsilon cdot T cdot D1}{D2 – D1} ]
This capacitance affects circuit performance by extending signal rise times and reducing overall circuit speed. For instance, in a PCB with a thickness of 50 mils, a via pad diameter of 20 mils (drilling diameter of 10 mils), and a solder mask opening diameter of 40 mils, the parasitic capacitance can be estimated using the formula:
[ C = 1.41 cdot frac{4.4 cdot 0.050 cdot 0.020}{0.040 – 0.020} = 0.31 text{ pF} ]
The rise time delay caused by this capacitance is approximately ( T_{10-90} = 2.2C left( frac{Z0}{2} right) = 17.05 text{ ps} ). While the delay caused by a single via may seem negligible, it becomes significant when multiple vias are used for interlayer connections in routing, necessitating careful consideration in design.
In practical design, reducing parasitic capacitance can be achieved by increasing the distance between vias and copper areas or by reducing pad diameters.
Inductance also exists in vias and can have a more detrimental effect in high-speed digital circuits compared to capacitance. The parasitic series inductance weakens the effectiveness of bypass capacitors and the overall filtering capability of the power supply system. An empirical formula to estimate the approximate parasitic inductance (L) of a via is:
[ L = 5.08h left[ ln left( frac{4h}{d} right) + 1 right] ]
Here, h is the via length and d is the central borehole diameter. Using the aforementioned example, the inductance of the via is calculated as:
[ L = 5.08 cdot 0.050 left[ ln left( frac{4 cdot 0.050}{0.010} right) + 1 right] = 1.015 text{ nH} ]
If the signal rise time is 1 ns, the corresponding impedance is ( X_L = pi L / T_{10-90} = 3.19 Omega ), which cannot be ignored for high-frequency current passage. This is particularly critical when connecting power layers with ground, where multiple vias may be necessary.
3. How to Use Vias
From the analysis of via parasitic characteristics, it is evident that in high-speed PCB designs, seemingly simple vias can significantly impact circuit performance negatively. To mitigate these effects, the following design measures are recommended:
1) **Optimize Via Size**: Choose via sizes based on cost and signal quality considerations. Different sizes may be used for power/ground vias (larger for lower impedance) versus signal vias (smaller).
2) **PCB Thickness**: Thinner PCBs help reduce both parasitic capacitance and inductance of vias.
3) **Minimize Layer Changes**: Avoid unnecessary vias for signal routing to maintain signal integrity.
4) **Proximity of Power/Ground Pins**: Place vias close to power and ground pins with short leads to minimize inductance. Consider parallel vias to further reduce equivalent inductance.
5) **Grounding Vias**: Place grounded vias near signal vias to provide a nearby return path for signals. Additional redundant grounding vias can be beneficial.
6) **Micro Vias**: In dense high-speed PCBs, consider using micro vias to mitigate parasitic effects.
These measures help optimize via usage and mitigate the negative impacts of parasitic effects in high-speed PCB designs.
Through-holes are integral to multilayer PCBs, with drilling costs typically comprising 30% to 40% of manufacturing expenses. Essentially, each hole in a PCB serves as a via. Functionally, vias fall into two categories: one facilitates electrical connections between layers, while the other secures or positions components. Technologically, these vias are generally classified into three types: blind vias, buried vias, and through-holes.
2. Blind holes are situated on the top and bottom PCB surfaces, penetrating to a specified depth to link surface and internal circuitry. Buried vias connect inner layers without extending to the board surface. Both types are prepared pre-lamination through hole formation, often overlapping multiple inner layers. Through-holes traverse the entire board, serving internal connections or component mounting, favored for their technical feasibility and cost efficiency.
3. By design, a via comprises a central drill hole and surrounding pad area, dictating its size. In high-speed, high-density PCB design, smaller vias are preferred to maximize board wiring space and minimize parasitic capacitance, critical for high-speed circuits. However, reducing via size escalates costs and is constrained by drilling and plating capabilities: smaller holes increase drilling time and risk center deviation, while holes deeper than 6 times their diameter pose uniform copper plating challenges.
4. With advancements in laser drilling, hole sizes continue to shrink, with diameters ≤ 6 mils termed microvias. Integral to HDI designs, microvias punched directly on pads enhance circuit performance and conserve wiring space. Vias on transmission lines act as impedance-disrupting breakpoints, inducing signal reflections. Typically, via impedance is about 12% lower than transmission lines, causing a minimal reflection coefficient (e.g., (44-50)/(44+50)=0.06). Concerns center on parasitic capacitance and inductance effects rather than significant reflection issues.
2. Parasitic Capacitance and Inductance of Vias
There are parasitic stray capacitance and inductance associated with vias. The capacitance mainly arises within the via itself. If we know the diameter of the solder mask opening around the via (D2), the diameter of the via pad (D1), the PCB thickness (T), and the dielectric constant of the PCB substrate (ε), then the parasitic capacitance (C) of the via can be approximated as:
[ C = 1.41 cdot frac{epsilon cdot T cdot D1}{D2 – D1} ]
This capacitance affects circuit performance by extending signal rise times and reducing overall circuit speed. For instance, in a PCB with a thickness of 50 mils, a via pad diameter of 20 mils (drilling diameter of 10 mils), and a solder mask opening diameter of 40 mils, the parasitic capacitance can be estimated using the formula:
[ C = 1.41 cdot frac{4.4 cdot 0.050 cdot 0.020}{0.040 – 0.020} = 0.31 text{ pF} ]
The rise time delay caused by this capacitance is approximately ( T_{10-90} = 2.2C left( frac{Z0}{2} right) = 17.05 text{ ps} ). While the delay caused by a single via may seem negligible, it becomes significant when multiple vias are used for interlayer connections in routing, necessitating careful consideration in design.
In practical design, reducing parasitic capacitance can be achieved by increasing the distance between vias and copper areas or by reducing pad diameters.
Inductance also exists in vias and can have a more detrimental effect in high-speed digital circuits compared to capacitance. The parasitic series inductance weakens the effectiveness of bypass capacitors and the overall filtering capability of the power supply system. An empirical formula to estimate the approximate parasitic inductance (L) of a via is:
[ L = 5.08h left[ ln left( frac{4h}{d} right) + 1 right] ]
Here, h is the via length and d is the central borehole diameter. Using the aforementioned example, the inductance of the via is calculated as:
[ L = 5.08 cdot 0.050 left[ ln left( frac{4 cdot 0.050}{0.010} right) + 1 right] = 1.015 text{ nH} ]
If the signal rise time is 1 ns, the corresponding impedance is ( X_L = pi L / T_{10-90} = 3.19 Omega ), which cannot be ignored for high-frequency current passage. This is particularly critical when connecting power layers with ground, where multiple vias may be necessary.
3. How to Use Vias
From the analysis of via parasitic characteristics, it is evident that in high-speed PCB designs, seemingly simple vias can significantly impact circuit performance negatively. To mitigate these effects, the following design measures are recommended:
1) **Optimize Via Size**: Choose via sizes based on cost and signal quality considerations. Different sizes may be used for power/ground vias (larger for lower impedance) versus signal vias (smaller).
2) **PCB Thickness**: Thinner PCBs help reduce both parasitic capacitance and inductance of vias.
3) **Minimize Layer Changes**: Avoid unnecessary vias for signal routing to maintain signal integrity.
4) **Proximity of Power/Ground Pins**: Place vias close to power and ground pins with short leads to minimize inductance. Consider parallel vias to further reduce equivalent inductance.
5) **Grounding Vias**: Place grounded vias near signal vias to provide a nearby return path for signals. Additional redundant grounding vias can be beneficial.
6) **Micro Vias**: In dense high-speed PCBs, consider using micro vias to mitigate parasitic effects.
These measures help optimize via usage and mitigate the negative impacts of parasitic effects in high-speed PCB designs.
