In PCB design, we typically prioritize signal quality, but often focus solely on the signal lines while treating power and ground as ideal conditions. While this approach simplifies the issue, it’s no longer viable in high-speed designs, particularly in China. Although circuit design directly influences signal integrity, we must not overlook power integrity, as it significantly impacts the final PCB’s signal quality. Power integrity and signal integrity are closely intertwined; frequently, signal distortion originates from the power system. Issues such as excessive ground bounce noise, inappropriate decoupling capacitor design, severe loop effects, poor separation of power/ground planes, unreasonable ground layer design, and uneven current distribution all contribute to this.
1) Decoupling Capacitor
It’s widely accepted that adding capacitors between the power supply and ground can mitigate system noise. However, questions remain: How many capacitors should we place on the circuit board? What capacitance values are ideal for each? What are the optimal positions for these capacitors? Often, these considerations are overlooked, relying instead on designer experience, with some even believing that less capacitance is preferable. In high-speed design, we must account for the parasitic parameters of capacitors, quantitatively determining the necessary number, capacitance values, and precise placements to ensure system impedance remains manageable. A fundamental principle is that all required decoupling capacitors should be included, with neither deficits nor excess.
2) Ground Bounce
When the edge rate of a high-speed device is less than 0.5 ns, the data exchange rate from a high-capacity data bus is exceedingly rapid. This can create significant ripples in the power layer that affect signal stability, leading to power instability issues. As current flows through the ground loop, voltage is induced due to loop inductance. A shortened rising edge increases the current change rate, thereby elevating ground bounce voltage. At this point, the ground plane is no longer at an ideal zero level, nor is the power supply a perfect DC potential. As more gates switch simultaneously, ground bounce worsens. For instance, in a 128-bit bus, up to 50-100 I/O lines may switch at the same clock edge. Therefore, the inductance of the power and ground loops returning to simultaneously switching I/O drivers must be minimized; otherwise, voltage spikes can occur when connected to a common ground. Ground bounce is prevalent in chips, packages, connectors, and circuit boards, potentially leading to significant power integrity issues.
1) From a technological development perspective, the rising edge of devices will only diminish, while the width of the bus will continue to expand. The sole method to maintain ground bounce at an acceptable level is to minimize the inductance of power and ground distribution. For the chip, this entails transitioning to an array configuration, maximizing the number of power and ground connections, and ensuring the wiring to the package is as short as possible to reduce inductance.
2) Regarding packaging, this involves shifting to a layered approach that brings the power and ground planes closer together, as seen in BGA packaging. For connectors, it means incorporating more ground pins or redesigning them to include an internal power supply and ground plane, such as with a connector-based ribbon cord. In terms of the circuit board, it necessitates positioning adjacent power and ground planes as closely as feasible. Since inductance is proportional to length, minimizing the distance between the power supply and ground will effectively reduce ground noise.
3) Power distribution system
In PCB layout and design, ensuring power integrity is a complex challenge. However, controlling the impedance between the power supply system (including the power supply and ground plane) has become crucial in recent years. Ideally, lower impedance results in reduced noise amplitude and voltage loss. In practice, we can establish a target impedance by defining the maximum voltage and power supply range we aim for, and then adjusting the relevant factors in the circuit to bring the impedance of each segment of the power system (frequency-related) closer to this target.
1) Decoupling Capacitor
It’s widely accepted that adding capacitors between the power supply and ground can mitigate system noise. However, questions remain: How many capacitors should we place on the circuit board? What capacitance values are ideal for each? What are the optimal positions for these capacitors? Often, these considerations are overlooked, relying instead on designer experience, with some even believing that less capacitance is preferable. In high-speed design, we must account for the parasitic parameters of capacitors, quantitatively determining the necessary number, capacitance values, and precise placements to ensure system impedance remains manageable. A fundamental principle is that all required decoupling capacitors should be included, with neither deficits nor excess.
2) Ground Bounce
When the edge rate of a high-speed device is less than 0.5 ns, the data exchange rate from a high-capacity data bus is exceedingly rapid. This can create significant ripples in the power layer that affect signal stability, leading to power instability issues. As current flows through the ground loop, voltage is induced due to loop inductance. A shortened rising edge increases the current change rate, thereby elevating ground bounce voltage. At this point, the ground plane is no longer at an ideal zero level, nor is the power supply a perfect DC potential. As more gates switch simultaneously, ground bounce worsens. For instance, in a 128-bit bus, up to 50-100 I/O lines may switch at the same clock edge. Therefore, the inductance of the power and ground loops returning to simultaneously switching I/O drivers must be minimized; otherwise, voltage spikes can occur when connected to a common ground. Ground bounce is prevalent in chips, packages, connectors, and circuit boards, potentially leading to significant power integrity issues.
1) From a technological development perspective, the rising edge of devices will only diminish, while the width of the bus will continue to expand. The sole method to maintain ground bounce at an acceptable level is to minimize the inductance of power and ground distribution. For the chip, this entails transitioning to an array configuration, maximizing the number of power and ground connections, and ensuring the wiring to the package is as short as possible to reduce inductance.
2) Regarding packaging, this involves shifting to a layered approach that brings the power and ground planes closer together, as seen in BGA packaging. For connectors, it means incorporating more ground pins or redesigning them to include an internal power supply and ground plane, such as with a connector-based ribbon cord. In terms of the circuit board, it necessitates positioning adjacent power and ground planes as closely as feasible. Since inductance is proportional to length, minimizing the distance between the power supply and ground will effectively reduce ground noise.
3) Power distribution system
In PCB layout and design, ensuring power integrity is a complex challenge. However, controlling the impedance between the power supply system (including the power supply and ground plane) has become crucial in recent years. Ideally, lower impedance results in reduced noise amplitude and voltage loss. In practice, we can establish a target impedance by defining the maximum voltage and power supply range we aim for, and then adjusting the relevant factors in the circuit to bring the impedance of each segment of the power system (frequency-related) closer to this target.
