1. Strictly control the length of key network cables
When designing high-speed PCBs, the transmission line effect can lead to significant signal integrity issues. This problem becomes more pronounced with modern integrated circuit chips operating at very high clock frequencies. To mitigate these issues, follow these guidelines: For CMOS or TTL circuits with an operating frequency below 10 MHz, the trace length should not exceed 7 inches. For a frequency of 50 MHz, keep the trace length to a maximum of 1.5 inches. If the frequency reaches or exceeds 75 MHz, the trace length should be limited to 1 inch. For GaAs chips, the trace length should be no more than 0.3 inches. Exceeding these lengths may result in transmission line problems.
2. **Reasonably plan the topology of the traces**
Another way to address transmission line effects is to choose the correct routing path and termination topology. The topology of the wiring refers to the sequence and structure of the network cable. When using high-speed logic devices, unless trace branch lengths are kept short, signals with rapidly changing edges will be distorted by branch traces on the signal trunk trace. Typically, two basic topologies are used for PCB routing: Daisy Chain and Star distribution. For daisy-chain wiring, the routing starts from the driver and proceeds to the receivers sequentially. If series resistors are used to alter the signal characteristics, they should be placed close to the drive terminals. In terms of controlling high-order harmonic interference, daisy-chain wiring performs well. However, achieving a 100% routing rate with this method can be challenging. In practice, we make the branch lengths in daisy chain wiring as short as possible; the safe length value should be considered. Star topology can effectively avoid clock signal asynchrony but is challenging to implement manually on high-density PCBs. An autorouter is often used for star wiring. Terminating resistors are required on each branch, with values matching the characteristic impedance of the connection. This can be calculated manually or using CAD tools. While simple termination resistors were used in the above examples, more complex matched terminations could be employed in practice. RC matching termination, for example, reduces power consumption but is only suitable for relatively stable signal operations, like clock lines. However, capacitance in RC matching can affect signal shape and speed. Series resistor-matched termination avoids additional power dissipation but slows down signal transmission, making it suitable for bus drive circuits where time delay is less critical. The advantage of series resistor matching is its potential to reduce the number of components and wiring density on the board. Matching terminals can be separated, with components placed near the receiving end to avoid pulling down the signal and minimizing noise. This approach is typical for TTL input signals (ACT, HCT, FAST). Additionally, the package type and mounting method of termination resistors are crucial. SMD resistors generally have lower inductance compared to through-hole components. For in-line resistors, vertical mounting provides shorter thermal resistance but increases inductance, while horizontal mounting offers lower inductance but can lead to resistor drift and potential open circuit issues.
3. **Methods of Suppressing Electromagnetic Interference**
A good solution for signal integrity will enhance the electromagnetic compatibility (EMC) of the PCB. Ensuring proper grounding is critical. Using a signal layer with a ground plane is highly effective for complex designs. Additionally, increasing the signal density on the outer layer of the circuit board helps reduce electromagnetic radiation. This can be achieved through “surface area layer” technology in a “Build-up” design. The surface area layer involves adding thin insulating layers and micro vias to penetrate these layers on a common process PCB. Resistors and capacitors can be buried under the surface layer, doubling the trace density per unit area and reducing PCB volume. The reduction in PCB area significantly impacts trace topology, leading to shorter current loops and reduced electromagnetic radiation, which is proportional to the area of the current loop. Smaller volumes also enable the use of high-density lead-packed devices, further reducing wire lengths, current loops, and improving EMC.
4. **Other Technologies That Can Be Used**
To reduce transient overshoot of the voltage on integrated circuit chips, decoupling capacitors should be added. These capacitors effectively mitigate glitches on the power supply and reduce radiation from the power loop on the PCB. Connecting the decoupling capacitor directly to the power pin of the integrated circuit, rather than to the power plane, enhances its ability to smooth glitches. This explains why some devices have decoupling capacitors on their sockets, while others require capacitors to be very close to the device. High-speed and high-power devices should be placed together to minimize transient overshoot. Long power traces without power planes can create loops between signals, becoming sources of radiation and susceptible circuits. A loop that does not pass through the same network cable or other traces is called an open loop, while a closed loop forms if it passes through other traces of the same network. Both scenarios create antenna effects (wire and loop antennas), which generate EMI radiation and are sensitive to circuit disturbances. Closing the loop is essential as it produces radiation proportional to the area of the closed loop on the PCB.
