For PCB designers, the inductance of vias is often more critical than capacitance. Each via introduces parasitic inductance into the circuit, and due to the small physical dimensions of vias, they behave like lumped circuit elements. The primary effect of the series inductance of vias is that it diminishes the efficiency of power supply bypass capacitors, thus negatively impacting the overall filtering effectiveness of the power system.
The primary purpose of a bypass capacitor is to provide a low impedance path between the power and ground planes at high frequencies. To illustrate, assume there is an integrated circuit (IC) connected between the power supply and ground at point A, and an ideal surface-mount bypass capacitor is placed at point B. In an ideal scenario, the high-frequency impedance between the Vcc of the chip bonding point and the ground plane would be zero. However, this is not the case in reality. Each via that connects the capacitor to the Vcc and ground planes introduces a small but measurable inductance.
The inductance of a via can be approximated using the following formula:
[
L = f(H, D)
]
Where:
– (L) is the inductance of the via in nanohenries (nH)
– (H) is the length of the via in inches
– (D) is the diameter of the via in inches
It’s important to note that since the formula includes a logarithmic term, changes in the diameter of the via have minimal impact on the inductance. However, variations in the via length can result in significant changes in inductance.
To further illustrate, consider the effect of via inductance on a signal with a rising edge speed of 1ns. The inductance value can be calculated using the appropriate formulas for the specific via dimensions. This helps determine the overall effect on signal integrity and the high-frequency performance of the PCB, emphasizing the importance of minimizing via inductance for better power integrity and signal fidelity.
In summary, when designing PCBs, the impact of via inductance should not be underestimated. Its contribution to the overall impedance network can degrade the performance of high-speed signals and power delivery systems. Therefore, careful consideration of via length, diameter, and placement can significantly enhance the overall PCB performance.
**Through-Hole Impedance and Bypass Capacitor Considerations in High-Frequency PCB Design**
**Key Parameters:**
– **H = 0.063 in** (Length of the through hole)
– **D = 0.016 in** (Through hole diameter)
– **T10~90% = 1.00 ns** (Rising edge speed)
**Overview:**
In high-frequency PCB designs, the impedance introduced by through-holes and vias can have a significant impact on signal integrity. One of the most common sources of impedance is the inductance of through-holes, especially when used for connecting bypass capacitors between the power and ground planes. This article explores how to manage this impedance and optimize bypass capacitor performance.
### **Inductive Effects of Through-Holes**
At high frequencies, the current that flows from the chip is shunted by bypass capacitors, which are typically connected between the power and ground planes. However, the effectiveness of this bypassing can be compromised if the inductance of the vias is not properly considered. In this case, the via inductance can be more problematic than the resistance of the capacitor itself, especially when the impedance of the through-hole is relatively high, such as 3.8 ohms.
**Impact of Inductance:**
– **Through-hole inductance doubles** because each end of the bypass capacitor is connected to a separate plane via a through-hole (one to the ground plane and the other to the +5V plane).
– The **placement of the bypass capacitor** should be as close to the power and ground planes as possible to minimize the inductive effects. Ideally, it should be positioned on the side of the board closest to these planes.
### **Minimizing Inductive Impacts**
While the placement of the capacitor is crucial, the traces connecting the capacitor to the vias also contribute to the overall inductance. Therefore, these traces should always be made as wide as possible to reduce their inductive impedance.
### **Using Multiple Bypass Capacitors**
To achieve a low impedance between the power supply and ground, **multiple bypass capacitors** are often used in parallel. For digital circuits, we can approximate the power and ground planes as ideal conductors with zero inductance. The primary inductive effects are then attributed to the bypass capacitors, their vias, and their associated traces.
**Key Insight:**
– **Inductive Effect of Multiple Capacitors:** When multiple bypass capacitors are placed between the power supply and ground, they act collectively to reduce the impedance. However, this effect is most pronounced within a specific range of distances.
– The **effective radius** for this parallel effect is approximately 1/12 of the electrical length of the rising edge. In simpler terms, capacitors within 1/6 of the rising edge diameter will effectively behave as a lumped circuit, providing optimal bypass performance.
### **Consideration of Rising Edge Speed and PCB Grid Spacing**
For an edge speed of 1 ns, the propagation length in FR-4 material is approximately 1/6 in (0.167 inches). This means that for bypass capacitors spaced further than **1/12 = 0.5 in** from each other, there will be no significant benefit in terms of impedance reduction.
### **Effect of Rise Time on Bypass Capacitor Performance**
A crucial factor in bypass capacitor performance is the **rise time** of the signal. The shorter the rise time, the more difficult it becomes to achieve effective bypassing. This is because as rise time shortens:
– The **effective radius** for bypass capacitors decreases.
– The number of capacitors within this effective radius diminishes, following a squared relationship with the rise time.
### **Impact on Frequency and Inductance**
As the rise time decreases, the **digital corner frequency** increases, which results in higher inductance from each via. This inductive increase reduces the effectiveness of the bypass capacitor. For example, if the rise time is halved, the impact of the bypass capacitor at a given frequency will decrease by a factor of 8.
**Key Takeaway:**
– When a PCB factory reduces the rise time by half, the efficiency of a bypass capacitor in a specific frequency range will be reduced by a factor of 8. This scaling can be used to predict the behavior of capacitors at different frequencies, allowing designers to optimize capacitor selection based on the operating frequency range.
### **Conclusion**
In summary, careful consideration of through-hole inductance, bypass capacitor placement, and trace design is essential for optimizing high-frequency performance in PCB layouts. The use of multiple capacitors in parallel, combined with optimal placement and trace widths, can minimize impedance and improve signal integrity. Furthermore, understanding the relationship between rise time, frequency, and capacitor performance helps ensure that the PCB design will function effectively across the desired frequency range.
The primary purpose of a bypass capacitor is to provide a low impedance path between the power and ground planes at high frequencies. To illustrate, assume there is an integrated circuit (IC) connected between the power supply and ground at point A, and an ideal surface-mount bypass capacitor is placed at point B. In an ideal scenario, the high-frequency impedance between the Vcc of the chip bonding point and the ground plane would be zero. However, this is not the case in reality. Each via that connects the capacitor to the Vcc and ground planes introduces a small but measurable inductance.
The inductance of a via can be approximated using the following formula:
[
L = f(H, D)
]
Where:
– (L) is the inductance of the via in nanohenries (nH)
– (H) is the length of the via in inches
– (D) is the diameter of the via in inches
It’s important to note that since the formula includes a logarithmic term, changes in the diameter of the via have minimal impact on the inductance. However, variations in the via length can result in significant changes in inductance.
To further illustrate, consider the effect of via inductance on a signal with a rising edge speed of 1ns. The inductance value can be calculated using the appropriate formulas for the specific via dimensions. This helps determine the overall effect on signal integrity and the high-frequency performance of the PCB, emphasizing the importance of minimizing via inductance for better power integrity and signal fidelity.
In summary, when designing PCBs, the impact of via inductance should not be underestimated. Its contribution to the overall impedance network can degrade the performance of high-speed signals and power delivery systems. Therefore, careful consideration of via length, diameter, and placement can significantly enhance the overall PCB performance.
**Through-Hole Impedance and Bypass Capacitor Considerations in High-Frequency PCB Design**
**Key Parameters:**
– **H = 0.063 in** (Length of the through hole)
– **D = 0.016 in** (Through hole diameter)
– **T10~90% = 1.00 ns** (Rising edge speed)
**Overview:**
In high-frequency PCB designs, the impedance introduced by through-holes and vias can have a significant impact on signal integrity. One of the most common sources of impedance is the inductance of through-holes, especially when used for connecting bypass capacitors between the power and ground planes. This article explores how to manage this impedance and optimize bypass capacitor performance.
### **Inductive Effects of Through-Holes**
At high frequencies, the current that flows from the chip is shunted by bypass capacitors, which are typically connected between the power and ground planes. However, the effectiveness of this bypassing can be compromised if the inductance of the vias is not properly considered. In this case, the via inductance can be more problematic than the resistance of the capacitor itself, especially when the impedance of the through-hole is relatively high, such as 3.8 ohms.
**Impact of Inductance:**
– **Through-hole inductance doubles** because each end of the bypass capacitor is connected to a separate plane via a through-hole (one to the ground plane and the other to the +5V plane).
– The **placement of the bypass capacitor** should be as close to the power and ground planes as possible to minimize the inductive effects. Ideally, it should be positioned on the side of the board closest to these planes.
### **Minimizing Inductive Impacts**
While the placement of the capacitor is crucial, the traces connecting the capacitor to the vias also contribute to the overall inductance. Therefore, these traces should always be made as wide as possible to reduce their inductive impedance.
### **Using Multiple Bypass Capacitors**
To achieve a low impedance between the power supply and ground, **multiple bypass capacitors** are often used in parallel. For digital circuits, we can approximate the power and ground planes as ideal conductors with zero inductance. The primary inductive effects are then attributed to the bypass capacitors, their vias, and their associated traces.
**Key Insight:**
– **Inductive Effect of Multiple Capacitors:** When multiple bypass capacitors are placed between the power supply and ground, they act collectively to reduce the impedance. However, this effect is most pronounced within a specific range of distances.
– The **effective radius** for this parallel effect is approximately 1/12 of the electrical length of the rising edge. In simpler terms, capacitors within 1/6 of the rising edge diameter will effectively behave as a lumped circuit, providing optimal bypass performance.
### **Consideration of Rising Edge Speed and PCB Grid Spacing**
For an edge speed of 1 ns, the propagation length in FR-4 material is approximately 1/6 in (0.167 inches). This means that for bypass capacitors spaced further than **1/12 = 0.5 in** from each other, there will be no significant benefit in terms of impedance reduction.
### **Effect of Rise Time on Bypass Capacitor Performance**
A crucial factor in bypass capacitor performance is the **rise time** of the signal. The shorter the rise time, the more difficult it becomes to achieve effective bypassing. This is because as rise time shortens:
– The **effective radius** for bypass capacitors decreases.
– The number of capacitors within this effective radius diminishes, following a squared relationship with the rise time.
### **Impact on Frequency and Inductance**
As the rise time decreases, the **digital corner frequency** increases, which results in higher inductance from each via. This inductive increase reduces the effectiveness of the bypass capacitor. For example, if the rise time is halved, the impact of the bypass capacitor at a given frequency will decrease by a factor of 8.
**Key Takeaway:**
– When a PCB factory reduces the rise time by half, the efficiency of a bypass capacitor in a specific frequency range will be reduced by a factor of 8. This scaling can be used to predict the behavior of capacitors at different frequencies, allowing designers to optimize capacitor selection based on the operating frequency range.
### **Conclusion**
In summary, careful consideration of through-hole inductance, bypass capacitor placement, and trace design is essential for optimizing high-frequency performance in PCB layouts. The use of multiple capacitors in parallel, combined with optimal placement and trace widths, can minimize impedance and improve signal integrity. Furthermore, understanding the relationship between rise time, frequency, and capacitor performance helps ensure that the PCB design will function effectively across the desired frequency range.
