1. How to calculate the impedance of FPC?
FPC flexible boards are increasingly favored in various fields due to their lightweight, thin, and compact design. As many boards require component assembly or various signal transmissions, the demand for FPC impedance continues to rise. Impedance is generally influenced by four key factors: 1) DK value, 2) copper thickness, 3) copper trace width and spacing, and 4) dielectric layer thickness (PI & coverlay).
Er1: The DK value of the substrate varies across different material brands and thicknesses, typically ranging from 3.15 to 4.2.
T1: The thickness of the copper refers to the finished copper layer, indicated as 30µm in the table below, suggesting that the base copper thickness is approximately 18µm.
W1: The width of the copper trace is W1, while S1 denotes the spacing between traces. Both trace width and spacing significantly affect impedance.
H1: The thickness of the dielectric layer, specifically the PI of the substrate, along with the adhesion thickness between the PI and adhesive material, is crucial.
W1&S1: The width and spacing of copper traces.
C1 / C2 / C3: Cover layer thickness. A 1/2 mil cover layer measures 28 µm, while a 1 mil cover layer is 50 µm.
CEr: The dielectric constant (DK) of the cover layer is 2.45 for a 1/2 mil cover and 3.4 for a 1 mil cover.
Typically, customers require impedance values and the total board thickness (stacking). How do we achieve the impedance specified by clients?
The first step involves adjusting the copper traces and spacing to meet the required impedance. A narrower trace width results in a higher impedance. Our minimum for copper trace width and spacing is 2 mil. If impedance is still not achieved at this setting, we must proceed to the second step.
In the second step, the reference layer for impedance is usually copper foil; we can switch to grid copper, as larger grid spacing increases impedance values.
If the impedance requirements remain unmet after the first two steps, the third step is to collaborate with the customer to adjust the laminate, considering the thickness of copper, dielectric layer, and cover layer.
2. What causes residual copper after FPC etching?
FPC soft board materials are rolled prior to cutting, meaning the copper remains intact. The finished FPC we see is derived from a designed circuit diagram, and etching is used to retain the desired layout on the substrate. Residual copper post-etching occurs because the etching solution is evenly sprayed onto the copper foil at a specific temperature (45±5°C). When not protected by etching resist, copper undergoes an oxidation-reduction reaction, resulting in the removal of unnecessary copper and exposing the substrate to form the circuit after stripping. The etching solution consists of copper chloride, hydrogen peroxide, hydrochloric acid, and soft water (with strict solubility requirements).
1. Reasons for residual copper after etching:
1. Incomplete developing (dry film remnants in areas corresponding to residual copper); conduct a copper chloride test.
2. The film in the affected area may be transparent. First, check the film’s integrity and line clarity.
2. Methods to address residual copper post-etching:
1. For overall residual copper, assess the etching section, focusing on the temperature, concentration of the etching solution, nozzle pressure, and potential blockage. Testing the etching breakpoint distance is advisable, as proper copper orientation aids in corrosion.
2. Residual copper in line spacing also relates to dry film selection.
3. For partial residual copper, examine the exposure and development phases.
4. Analyze specific issues, targeting residual copper conditions in flexible circuit boards and adjusting the FPC etching production process accordingly.
FPC flexible boards are increasingly favored in various fields due to their lightweight, thin, and compact design. As many boards require component assembly or various signal transmissions, the demand for FPC impedance continues to rise. Impedance is generally influenced by four key factors: 1) DK value, 2) copper thickness, 3) copper trace width and spacing, and 4) dielectric layer thickness (PI & coverlay).
Er1: The DK value of the substrate varies across different material brands and thicknesses, typically ranging from 3.15 to 4.2.
T1: The thickness of the copper refers to the finished copper layer, indicated as 30µm in the table below, suggesting that the base copper thickness is approximately 18µm.
W1: The width of the copper trace is W1, while S1 denotes the spacing between traces. Both trace width and spacing significantly affect impedance.
H1: The thickness of the dielectric layer, specifically the PI of the substrate, along with the adhesion thickness between the PI and adhesive material, is crucial.
W1&S1: The width and spacing of copper traces.
C1 / C2 / C3: Cover layer thickness. A 1/2 mil cover layer measures 28 µm, while a 1 mil cover layer is 50 µm.
CEr: The dielectric constant (DK) of the cover layer is 2.45 for a 1/2 mil cover and 3.4 for a 1 mil cover.
Typically, customers require impedance values and the total board thickness (stacking). How do we achieve the impedance specified by clients?
The first step involves adjusting the copper traces and spacing to meet the required impedance. A narrower trace width results in a higher impedance. Our minimum for copper trace width and spacing is 2 mil. If impedance is still not achieved at this setting, we must proceed to the second step.
In the second step, the reference layer for impedance is usually copper foil; we can switch to grid copper, as larger grid spacing increases impedance values.
If the impedance requirements remain unmet after the first two steps, the third step is to collaborate with the customer to adjust the laminate, considering the thickness of copper, dielectric layer, and cover layer.
2. What causes residual copper after FPC etching?
FPC soft board materials are rolled prior to cutting, meaning the copper remains intact. The finished FPC we see is derived from a designed circuit diagram, and etching is used to retain the desired layout on the substrate. Residual copper post-etching occurs because the etching solution is evenly sprayed onto the copper foil at a specific temperature (45±5°C). When not protected by etching resist, copper undergoes an oxidation-reduction reaction, resulting in the removal of unnecessary copper and exposing the substrate to form the circuit after stripping. The etching solution consists of copper chloride, hydrogen peroxide, hydrochloric acid, and soft water (with strict solubility requirements).
1. Reasons for residual copper after etching:
1. Incomplete developing (dry film remnants in areas corresponding to residual copper); conduct a copper chloride test.
2. The film in the affected area may be transparent. First, check the film’s integrity and line clarity.
2. Methods to address residual copper post-etching:
1. For overall residual copper, assess the etching section, focusing on the temperature, concentration of the etching solution, nozzle pressure, and potential blockage. Testing the etching breakpoint distance is advisable, as proper copper orientation aids in corrosion.
2. Residual copper in line spacing also relates to dry film selection.
3. For partial residual copper, examine the exposure and development phases.
4. Analyze specific issues, targeting residual copper conditions in flexible circuit boards and adjusting the FPC etching production process accordingly.
