When designing with high-speed FPGAs, it is crucial to consider several design issues before and during board development. These include reducing system noise by filtering and distributing sufficient power evenly across all devices on the PCB, properly terminating signal lines to minimize reflections, minimizing crosstalk between traces on the board, reducing the effects of ground bounce and Vcc reduction (also known as Vcc sag), and correctly matching impedance on high-speed signal lines. Anyone designing an IC package for a very high-performance FPGA must pay special attention to the balance between signal integrity and versatility for all users and applications.
For example, Altera’s Stratix II GX devices in a 1,508-pin package operate down to 1.2V and feature 734 standard I/Os and 71 low-voltage differential signaling (LVDS) channels. It also has 20 high-speed transceivers that support data rates up to 6.375Gbps. This enables the architecture to support many high-speed networking and communication bus standards, including PCI Express and SerialLite II.
1. In PCB board design, users can reduce crosstalk by optimizing the pinout. Signal pins should be placed as close as possible to ground pins to minimize loop lengths within the package, especially for critical high-speed I/O. In high-speed systems, the primary source of crosstalk is inductive coupling between signal paths within the package. When the output transitions, the signal must find a return path through the power/ground plane. Current changes in the loop create magnetic fields that induce noise on other nearby I/O pins. This situation worsens when multiple outputs switch simultaneously. Smaller loops have lower inductance, so packages with power or ground pins close to each high-speed signal pin can minimize crosstalk effects on adjacent I/O pins.
2. To reduce board costs and enhance system signal integrity across all paths, meticulous design and construction of board materials, layer count (stacking), and layout are essential. Transmitting numerous signals from the FPGA across or around the board is a complex task that necessitates the use of EDA tools to optimize pinout and chip placement. Sometimes, opting for a slightly larger FPGA package can lower board costs by reducing the required number of layers and other processing constraints.
3. High-speed signal paths on PCB boards, represented by traces, are highly sensitive to interruptions such as vias between board layers and connectors. These interruptions reduce signal edge rates, causing reflections. Therefore, designers should minimize vias and via stubs. If vias are unavoidable, keep their lengths as short as possible. When routing differential signals, ensure each path of the pair shares identical via structures to mitigate interruption effects in common mode. If feasible, prefer blind vias over regular ones, or utilize back-drilling to minimize signal path interruptions.
4. For optimal clock signal integrity, adhere to these guidelines: Keep the clock signal on a single board layer as much as possible before routing to components, and consistently use a plane as the reference. Route fast edge signals along inner layers adjacent to the ground plane to manage impedance and minimize EMI. Properly terminate the clock signal to reduce reflections. Utilize point-to-point clock traces where feasible. Some FPGAs, like the Stratix II GX family, feature on-chip series termination resistors supporting various I/O standards, enhancing signal integrity by eliminating external components and simplifying board layout and design cycles.
5. In PCB layout, following specific guidelines for microstrip and stripline routing minimizes crosstalk. For instance, in a double-stripline layout, wiring is confined to two inner board layers with voltage reference surfaces on both sides. Adjacent layer boards employ orthogonal wiring techniques to maximize isolation between signal layers. Maintaining consistent material thickness and normalized spacing between signal and adjacent reference planes ensures requisite impedance. For microstrip or stripline routing, maintain trace spacing at least three times the dielectric layer thickness between routing layers, and use simulation tools to predict behavior.
6. To minimize common-mode noise effects on critical high-speed networks, prefer differential over single-ended topology. Attempt to match positive and negative pins within design limits. For single-ended signals, maintain adequate spacing (greater than three times the trace width) or utilize different board layers for routing (with orthogonal arrangements). Simulation tools are invaluable for verifying spacing requirements and minimizing parallel lengths between signal terminations.
7. Simultaneous switching noise, clock frequencies, and I/O data rates correlate with reduced output transitions and increased transient currents during signal discharge and charging. These currents can induce board-level ground bounce—a temporary rise or fall of ground voltage or Vcc. Configure unused I/O pins as outputs driven low to mitigate ground bounce. Distribute simultaneous transition output pins evenly across the FPGA I/O section. Use low slew rates at FPGA outputs when high edge rates are unnecessary. Placing Vcc between the ground planes of multilayer boards reduces high-speed trace effects across layers, ensuring efficient logic signal return on adjacent signal layers.
8. The advanced transceiver capabilities of FPGAs make them versatile system-on-chip components, yet they pose unique challenges for board designers. Frequency-dependent transmission losses, primarily due to skin effect and dielectric losses, are critical concerns. Skin effect, impacting conductor surfaces at high frequencies, reduces effective conduction area, while dielectric losses stem from interlayer capacitive effects. Dielectric loss predominates at higher frequencies, significantly affecting signal attenuation levels.
9. However, modern transceivers incorporate transmitter pre-emphasis and receiver equalization to counteract high-frequency channel distortions, enhancing signal integrity and relaxing trace length constraints. These techniques extend the viability of standard FR-4 materials for higher data rates. For instance, while FR-4 limits trace lengths to a few inches at 6.375Gbps, pre-emphasis and equalization can extend this to over 40 inches, effectively compensating for board losses. Integrated programmable features in high-performance FPGAs like Stratix II GX devices support dynamic adjustment of pre-emphasis and equalization levels, ensuring optimal signal performance under varying conditions.
10. Efficient board design minimizes electromagnetic interference (EMI) by eliminating “hot” signals and grounding references. Surface mount components further reduce EMI. Debugging and testing complex high-speed PCB designs present challenges beyond traditional methods, necessitating advanced tools such as JTAG with in-system programming and self-test capabilities. Maintaining JTAG test clock inputs aligned with system clocks and minimizing scan chain trace lengths between devices ensures effective testing.
11. Designing with embedded high-speed FPGAs demands extensive practice and understanding of FPGA capabilities, including pinout, board materials, stacking, layout, and termination modes. Leveraging pre-emphasis and equalization in transceivers enhances design reliability and manufacturability. Comprehensive simulation and analysis preemptively identify issues in PCB prototypes, streamlining development and reducing project stress.
This revision aims to maintain the technical depth while enhancing clarity and readability throughout the document.
