High-speed PCB design requires careful attention to several key issues:
1. The impact of wiring topology on signal integrity
Signal integrity challenges can emerge when signals travel along transmission lines on high-speed PCBs. Netizen Tongyang from STMicroelectronics posed a question: For a bus system (including address, data, and command lines) driving up to 4 or 5 devices (such as FLASH and SDRAM), when designing the PCB, the bus connects to each device sequentially—first to SDRAM, then to FLASH, and so on. This bus configuration resembles a star topology, where it branches from a central point to connect with each device. These two approaches present different implications for signal integrity.
The influence of PCB wiring topology on signal integrity primarily manifests in the varying signal arrival times at each node, as well as the inconsistent timing of reflected signals at certain nodes, which can lead to degraded signal quality. Generally, a star topology can promote consistent signal transmission and reflection delays by ensuring that several branches are of equal length, thereby enhancing signal quality. Before implementing this topology, it is crucial to evaluate the conditions of the signal topology nodes, understand the actual operating principles, and assess the wiring complexities involved.
Sure! Here’s the revised text:
1. Different buffers influence signal reflection in various ways, which means that a star topology cannot address the delays in the data address bus linked to FLASH and SDRAM, thereby compromising signal integrity. Moreover, high-speed signals typically pertain to communication between DSP and SDRAM, while the FLASH loading rate is relatively low. Consequently, in high-speed simulations, we focus solely on the waveform at the nodes where actual high-speed signals operate effectively, rather than monitoring the waveform at FLASH. Compared to daisy chain and other topologies, star topology complicates wiring, especially when numerous data address signals are involved.
2. The effect of pads on high-speed signals is significant. In PCB design, a via consists mainly of the central hole and the surrounding pads. An engineer, Fulonm, inquired about how pads influence high-speed signals. Li Baolong explained that pads indeed affect high-speed signals, similar to the influence of device packaging on performance. Analyzing the process reveals that once a signal exits the IC, it travels through the bonding wire, pins, package shell, pad, and solder before reaching the transmission line. Each joint can impact signal quality. However, it’s challenging to provide specific parameters for pads, solder, and pins, so package parameters in the IBIS model are generally employed to summarize them. This analysis is effective at lower frequencies, but for higher frequencies, standard simulations may lack precision. A current trend is to utilize IBIS’s V-I and V-T curves to characterize buffers, alongside SPICE models for package parameters.
3. Electromagnetic interference (EMI) originates from PCBs, making PCB design crucial for the electromagnetic compatibility (EMC) of electronic products. Emphasizing EMC/EMI in high-speed PCB design can shorten product development cycles and accelerate market entry. Consequently, many engineers focus on EMI suppression during discussions. For instance, Shu Jian from Wuxi Xiangsheng Medical Imaging Co., Ltd. highlighted significant clock signal harmonics observed during EMC testing, questioning whether special treatment is necessary for the power supply pins of clock-utilizing ICs. Connecting a decoupling capacitor to the power supply pin was suggested. Li Baolong noted that the three elements of EMC include the radiation source, transmission route, and victim. The propagation path can be categorized into space radiation and cable conduction. To mitigate harmonics, one must first examine the propagation method. Power supply decoupling addresses conduction mode propagation, while appropriate matching and shielding are also essential.
Filtering is an effective approach to mitigate EMC radiation through conduction. Additionally, considerations should be made regarding interference sources and victims. For interference sources, utilizing an oscilloscope to check for excessively rapid signal rising edges, reflections, overshoot, undershoot, or ringing is advisable; if present, matching may be necessary. Moreover, avoid 50% duty cycle signals, as they can produce excessive sub-harmonics and high-frequency components. For victims, implementing measures such as land coverage can be beneficial.
4. When it comes to RF routing, the choice between vias and bends is critical. Analyzing the return path of RF circuits differs from that of high-speed digital circuits. While both share characteristics as distributed parameter circuits and utilize Maxwell’s equations for analysis, RF circuits are analog, requiring control over both voltage V=V(t) and current I=I(t). In contrast, digital circuits focus solely on voltage changes V=V(t). Therefore, RF routing must consider not only signal return paths but also how routing affects current flow, including the impact of bends and vias. Additionally, most RF boards are single-sided or double-sided PCBs lacking complete plane layers; hence, return paths are dispersed across various grounds and power supplies surrounding the signal. Simulation requires 3D field extraction tools for analysis, while the reflow of vias necessitates specific examination. In contrast, high-speed digital circuit analysis typically involves multi-layer PCBs with complete plane layers, relying on 2D field extraction analysis and primarily addressing signal return flows in adjacent planes, treating vias as lumped parameter RLC components.
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1. The impact of wiring topology on signal integrity
Signal integrity challenges can emerge when signals travel along transmission lines on high-speed PCBs. Netizen Tongyang from STMicroelectronics posed a question: For a bus system (including address, data, and command lines) driving up to 4 or 5 devices (such as FLASH and SDRAM), when designing the PCB, the bus connects to each device sequentially—first to SDRAM, then to FLASH, and so on. This bus configuration resembles a star topology, where it branches from a central point to connect with each device. These two approaches present different implications for signal integrity.
The influence of PCB wiring topology on signal integrity primarily manifests in the varying signal arrival times at each node, as well as the inconsistent timing of reflected signals at certain nodes, which can lead to degraded signal quality. Generally, a star topology can promote consistent signal transmission and reflection delays by ensuring that several branches are of equal length, thereby enhancing signal quality. Before implementing this topology, it is crucial to evaluate the conditions of the signal topology nodes, understand the actual operating principles, and assess the wiring complexities involved.
Sure! Here’s the revised text:
1. Different buffers influence signal reflection in various ways, which means that a star topology cannot address the delays in the data address bus linked to FLASH and SDRAM, thereby compromising signal integrity. Moreover, high-speed signals typically pertain to communication between DSP and SDRAM, while the FLASH loading rate is relatively low. Consequently, in high-speed simulations, we focus solely on the waveform at the nodes where actual high-speed signals operate effectively, rather than monitoring the waveform at FLASH. Compared to daisy chain and other topologies, star topology complicates wiring, especially when numerous data address signals are involved.
2. The effect of pads on high-speed signals is significant. In PCB design, a via consists mainly of the central hole and the surrounding pads. An engineer, Fulonm, inquired about how pads influence high-speed signals. Li Baolong explained that pads indeed affect high-speed signals, similar to the influence of device packaging on performance. Analyzing the process reveals that once a signal exits the IC, it travels through the bonding wire, pins, package shell, pad, and solder before reaching the transmission line. Each joint can impact signal quality. However, it’s challenging to provide specific parameters for pads, solder, and pins, so package parameters in the IBIS model are generally employed to summarize them. This analysis is effective at lower frequencies, but for higher frequencies, standard simulations may lack precision. A current trend is to utilize IBIS’s V-I and V-T curves to characterize buffers, alongside SPICE models for package parameters.
3. Electromagnetic interference (EMI) originates from PCBs, making PCB design crucial for the electromagnetic compatibility (EMC) of electronic products. Emphasizing EMC/EMI in high-speed PCB design can shorten product development cycles and accelerate market entry. Consequently, many engineers focus on EMI suppression during discussions. For instance, Shu Jian from Wuxi Xiangsheng Medical Imaging Co., Ltd. highlighted significant clock signal harmonics observed during EMC testing, questioning whether special treatment is necessary for the power supply pins of clock-utilizing ICs. Connecting a decoupling capacitor to the power supply pin was suggested. Li Baolong noted that the three elements of EMC include the radiation source, transmission route, and victim. The propagation path can be categorized into space radiation and cable conduction. To mitigate harmonics, one must first examine the propagation method. Power supply decoupling addresses conduction mode propagation, while appropriate matching and shielding are also essential.
Filtering is an effective approach to mitigate EMC radiation through conduction. Additionally, considerations should be made regarding interference sources and victims. For interference sources, utilizing an oscilloscope to check for excessively rapid signal rising edges, reflections, overshoot, undershoot, or ringing is advisable; if present, matching may be necessary. Moreover, avoid 50% duty cycle signals, as they can produce excessive sub-harmonics and high-frequency components. For victims, implementing measures such as land coverage can be beneficial.
4. When it comes to RF routing, the choice between vias and bends is critical. Analyzing the return path of RF circuits differs from that of high-speed digital circuits. While both share characteristics as distributed parameter circuits and utilize Maxwell’s equations for analysis, RF circuits are analog, requiring control over both voltage V=V(t) and current I=I(t). In contrast, digital circuits focus solely on voltage changes V=V(t). Therefore, RF routing must consider not only signal return paths but also how routing affects current flow, including the impact of bends and vias. Additionally, most RF boards are single-sided or double-sided PCBs lacking complete plane layers; hence, return paths are dispersed across various grounds and power supplies surrounding the signal. Simulation requires 3D field extraction tools for analysis, while the reflow of vias necessitates specific examination. In contrast, high-speed digital circuit analysis typically involves multi-layer PCBs with complete plane layers, relying on 2D field extraction analysis and primarily addressing signal return flows in adjacent planes, treating vias as lumped parameter RLC components.
If you have any PCB manufacturing needs, please do not hesitate to contact me.Contact me
