There are various methods to address EMI (Electromagnetic Interference) issues. Modern techniques for EMI suppression include the use of EMI shielding coatings, selecting appropriate EMI suppression components, and conducting EMI simulation during the design phase. This article begins with fundamental PCB layout principles and explores the role and design strategies of PCB layer stack-ups in controlling EMI radiation.

Power Bus Design

Strategically placing a capacitor of the correct capacitance value near the power supply pin of the IC can improve the IC’s output voltage response. However, this solution alone is not sufficient. Due to the limited frequency response of the capacitor, it cannot generate the harmonic energy required to ensure clean driving of the IC’s output across the entire frequency spectrum. Furthermore, transient voltages on the power bus can cause voltage drops across the inductance of the decoupling path. These transient voltages are a significant source of common-mode EMI interference. So, how can we address these challenges?

For the IC on a PCB, the power supply layer surrounding the IC acts as an excellent high-frequency capacitor. It can capture the energy that leaks from the discrete capacitor and provide the necessary high-frequency energy for clean output. Additionally, the inductance of a well-designed power layer should be low, thus minimizing the transient signals generated by the inductance and reducing common-mode EMI.

It is also essential to minimize the length of the wiring between the power supply layer and the IC power pin. As digital signal rise times continue to decrease, it is best to make this connection as short as possible, ideally directly to the pad of the IC power pin, which will be discussed further.

To effectively control common-mode EMI, the power layer should help decouple signals and have low inductance. The quality of the power layer depends on factors such as layer stack-up, materials between layers, and the operating frequency (which is influenced by the rise time of the IC). Generally, a power layer spacing of 6 mils and FR4 material between layers provides an equivalent capacitance of approximately 75 pF per square inch. The smaller the spacing between layers, the higher the capacitance.

Devices with a rise time of 100 to 300 ps are rare, but as IC technology advances, such devices will become more common. For circuits with rise times in the 100 to 300 ps range, 3 mil layer spacing may no longer be suitable for most applications. In such cases, a layer stack-up with less than 1 mil layer spacing and high-dielectric materials, such as ceramics, may be required to meet design needs.

Although new materials and methods may be introduced in the future, for current circuits with rise times between 1 to 3 ns, using 3 to 6 mil layer spacing and FR4 dielectric materials is typically sufficient to manage high-end harmonics and minimize transient signals, significantly reducing common-mode EMI. The design example discussed here assumes a layer spacing of 3 to 6 mils.

Electromagnetic Shielding

From the perspective of signal routing, a good layering strategy places all signal traces on one or more layers that are adjacent to the power or ground layers. For the power supply, a good layering strategy places the power layer adjacent to the ground layer, with minimal spacing between them. This is referred to as the “layering” strategy.

PCB Stack-up Design

What stack-up strategy helps shield and suppress EMI effectively? The following stack-up design assumes that the supply current flows on a single layer, and a single or multiple voltage sources are distributed across different areas of the same layer. Multiple power planes will be discussed later.

4-Layer PCB

A traditional 4-layer PCB design may present several challenges. For instance, with a 62-mil thick PCB, even if the signal layer is placed on the outer layer and the power and ground layers on the inner layers, the distance between the power and ground layers may still be too large.

If cost constraints are a priority, two alternatives to traditional 4-layer designs can be considered. Both options improve EMI suppression performance but are only suitable for boards with low component density and sufficient space around components (to accommodate the required power copper layer).

• The preferred option has outer layers as ground layers, with the middle two layers serving as signal/power layers. The power supply traces on the signal layer are routed with wide traces, minimizing the impedance of the power supply path and signal microstrip path. From an EMI control perspective, this is the best 4-layer PCB structure.
• The second option uses power and ground on the outer layers, with signal traces on the inner layers. While this solution provides some improvement, it is not as effective as the first option, and the interlayer impedance is suboptimal compared to traditional 4-layer boards.

If trace impedance control is essential, the above stacking schemes must ensure that traces are placed under the power and ground copper areas. Additionally, copper islands on power or ground planes should be interconnected to ensure proper DC and low-frequency connectivity.

6-Layer PCB

If the component density on a 4-layer PCB is high, a 6-layer PCB is often a better choice. However, some stack-up configurations in 6-layer designs are not effective at shielding electromagnetic fields and may have limited impact on reducing transient signals in the power bus. Two common scenarios are outlined below:

• In the first scenario, the power supply and ground are placed on the second and fifth layers, respectively. While this configuration offers good signal impedance control, the high copper resistance in the power supply layer makes it less effective for controlling common-mode EMI radiation.
• In the second scenario, the power supply and ground are placed on the third and fourth layers, respectively. This design resolves the copper-clad impedance issue of the power supply, but the shielding performance of the first and sixth layers is poor, leading to increased differential-mode EMI. If the outer layers carry minimal signal traces and have short trace lengths (less than 1/20th of the highest harmonic wavelength), this design can mitigate differential-mode EMI. Copper-filled, trace-free areas on the outer layers, grounded at regular intervals, provide effective EMI suppression. The copper area should be connected to the internal ground plane at multiple points for optimal performance.

A well-designed high-performance 6-layer PCB typically places the first and sixth layers as ground layers, with the third and fourth layers handling power and ground. The middle two layers, being microstrip signal layers, offer excellent EMI suppression. The main disadvantage of this design is the limited number of trace layers. However, with short traces on the outer layers and copper filling in trace-free areas, the same design goals can be achieved with a traditional 6-layer PCB.

10-Layer PCB

In a 10- or 12-layer PCB, the thin insulation between layers results in low impedance, which, when stacked correctly, ensures excellent signal integrity. However, manufacturing 12-layer boards with a thickness of 62 mils is challenging, and only a few manufacturers are capable of producing such boards.

In a 10-layer design, allocating six layers for signal traces is not the most optimal solution due to the insulation layers separating the signal and loop layers. A more effective design places the signal layers adjacent to the loop layers. A typical stack-up arrangement for such a design might be: signal, ground, signal, signal, power, ground, signal, signal, ground, signal.

This configuration provides a solid current path for both the signal and its return current. The optimal trace routing strategy places the signal on one layer and the return current on an adjacent layer, such as routing the signal on the first layer, the return current on the second layer, and so on. This minimizes inductance and ensures a clean signal with reduced EMI.

Multiple Power Layers Design

If two power layers of the same voltage need to output significant current, the PCB should include two sets of power and ground planes. An insulation layer should be placed between each pair of power and ground planes to ensure equal impedance. Uneven impedance between power planes leads to uneven current distribution, larger transient voltages, and increased EMI.

If there are multiple power supply voltages on the board, each voltage source should have its own dedicated power and ground layers. Be sure to follow the manufacturer’s guidelines to maintain a balanced stack-up design.

Conclusion

This article focuses on circuit board layering and stack-up strategies for traditional 62-mil thick PCBs without blind or buried vias. The recommended stack-up design may not be ideal for circuit boards with different thicknesses or for boards using blind or buried vias, as their manufacturing processes differ.

Ultimately, the key to solving EMI issues is not the PCB’s thickness or the number of layers, but an excellent stack-up design that ensures proper bypassing and decoupling of the power bus, minimizes transient voltages, and shields the signal and power supply’s electromagnetic fields. The distance between paired layers should be as small as possible, and the signal trace should ideally be adjacent to its return ground layer. By adhering to these principles, a PCB can meet design requirements and effectively mitigate EMI.