1. With the continuous emergence of products utilizing large-scale integrated circuits, the installation and testing of corresponding PCB boards have become increasingly challenging.
2. Although the traditional in-circuit test technology persists for testing printed circuit boards, its efficacy is diminishing due to the miniaturization and packaging of chips.
3. A new test technology—Boundary Scan Test (BST)—has gradually emerged, finding adoption in most ASIC circuits and many medium-scale equipment designs.
4. BST adheres to the IEEE1149.1 standard and furnishes a comprehensive suite of testing solutions.
5. During actual testing, it eliminates the need for complex and expensive test equipment, providing a technology-agnostic testing approach.
6. The benefits of employing Boundary Scan Test technology in integrated circuit and printed circuit board design lie in its simplicity, significantly reducing test and diagnostic times during production, experimentation, use, and maintenance, thereby substantially cutting costs.
1. The basic composition of BST
The BST circuit complies with the IEEE1149.1 standard, consisting of the test access channel TAP and its components: the controller, instruction register (IR), and the test data register group (TDR). The test access channel TAP features a 5-pin connector (with one pin dedicated to reset). The TAP controller operates as a 16-state state machine, generating clock signals and various control signals (e.g., test, shift, capture, and update signals). These signals facilitate the shifting of instructions or test data into the corresponding registers and control the various operational states of the boundary scan test.
1.1 Test of the clock input terminal TCK
The TCK signal synchronizes the boundary scan portion of the integrated circuit (IC) with the system clock, enabling independent operation.
1.2 Test mode selection input TMS
TMS determines the operational state of the TAP controller. It must be established prior to the rising edge of TCK.
1.3 Test data input terminal TDI
Data serially inserted through TDI is shifted into the instruction register or the test data register upon the rising edge of the test clock pulse TCK. The TAP controller discerns whether the shifted data is an instruction or test data.
1.4 Test data output terminal TDO
At the falling edge of the test clock pulse TCK, data is serially output from the instruction register or the test data register via TDO. The TAP controller determines whether the serialized data corresponds to an instruction or test data.
2. PCB board test system
2.1 Test system structure
The hardware comprises a general PC, a BST tester, and a serial BST signal cable (a bus with 4 signals: 1 for TDI, 2 for TCK, 3 for TMS, and 4 for TDO). The tester interfaces with the PC through a standard parallel port and with the test access port TAP on the PCB via a serial signal cable. If the PCB contains multiple modules (e.g., A, B, and C), each module, whether composed of a single chip or multiple chips, is designed in compliance with the IEEE1149.1 standard. This involves adding a BS register to the I/O pin of the chip(s) to enable boundary scan testing. Serial signal cables facilitate interconnection among multiple PCBs, allowing users to flexibly select chips, modules, or the entire PCB for testing via programming.
2.2 Principle of the test system
Testers utilize PC software programming to automatically generate test patterns for circuit fault detection based on the netlist and device model of the PCB. The PC should feature at least two boards with 32-bit I/O pins each, facilitating read and write operations. The test software comprises preprocessors and execution units. Preprocessors analyze test graphs to derive possible relationships, resulting in a set of files containing storage and control information. The execution unit loads these files to execute tests, involving reading stored information, inputting data to the appropriate ports, reading data from output ports, and comparing it with expected results. Fault detection triggers marking and location identification, supplemented by diagnostic programs for precise fault localization.
2.3 Test content
1) Testing the connectivity of the PCB’s I/O pins, crucial for providing access channels to the tester.
2) Verifying the integrity of IC chips on the PCB, assessing potential damage incurred during the chip assembly process via built-in self-tests and internal tests.
3) Identifying open circuit and short circuit faults in IC chip interconnections on the PCB, validated through external tests.
4) Assessing the integrity of the bus on the PCB to detect open circuit faults on the I/O pins of IC chips connected to the bus.
As BST technology advances, PCB testing continues to improve, benefiting from the widespread adoption of programmable integrated circuits. This enhances the flexibility and applicability of PCB testing while reducing associated test system costs. Designers can leverage programmable logic integrated circuits to create versatile PCBs
2. Although the traditional in-circuit test technology persists for testing printed circuit boards, its efficacy is diminishing due to the miniaturization and packaging of chips.
3. A new test technology—Boundary Scan Test (BST)—has gradually emerged, finding adoption in most ASIC circuits and many medium-scale equipment designs.
4. BST adheres to the IEEE1149.1 standard and furnishes a comprehensive suite of testing solutions.
5. During actual testing, it eliminates the need for complex and expensive test equipment, providing a technology-agnostic testing approach.
6. The benefits of employing Boundary Scan Test technology in integrated circuit and printed circuit board design lie in its simplicity, significantly reducing test and diagnostic times during production, experimentation, use, and maintenance, thereby substantially cutting costs.
1. The basic composition of BST
The BST circuit complies with the IEEE1149.1 standard, consisting of the test access channel TAP and its components: the controller, instruction register (IR), and the test data register group (TDR). The test access channel TAP features a 5-pin connector (with one pin dedicated to reset). The TAP controller operates as a 16-state state machine, generating clock signals and various control signals (e.g., test, shift, capture, and update signals). These signals facilitate the shifting of instructions or test data into the corresponding registers and control the various operational states of the boundary scan test.
1.1 Test of the clock input terminal TCK
The TCK signal synchronizes the boundary scan portion of the integrated circuit (IC) with the system clock, enabling independent operation.
1.2 Test mode selection input TMS
TMS determines the operational state of the TAP controller. It must be established prior to the rising edge of TCK.
1.3 Test data input terminal TDI
Data serially inserted through TDI is shifted into the instruction register or the test data register upon the rising edge of the test clock pulse TCK. The TAP controller discerns whether the shifted data is an instruction or test data.
1.4 Test data output terminal TDO
At the falling edge of the test clock pulse TCK, data is serially output from the instruction register or the test data register via TDO. The TAP controller determines whether the serialized data corresponds to an instruction or test data.
2. PCB board test system
2.1 Test system structure
The hardware comprises a general PC, a BST tester, and a serial BST signal cable (a bus with 4 signals: 1 for TDI, 2 for TCK, 3 for TMS, and 4 for TDO). The tester interfaces with the PC through a standard parallel port and with the test access port TAP on the PCB via a serial signal cable. If the PCB contains multiple modules (e.g., A, B, and C), each module, whether composed of a single chip or multiple chips, is designed in compliance with the IEEE1149.1 standard. This involves adding a BS register to the I/O pin of the chip(s) to enable boundary scan testing. Serial signal cables facilitate interconnection among multiple PCBs, allowing users to flexibly select chips, modules, or the entire PCB for testing via programming.
2.2 Principle of the test system
Testers utilize PC software programming to automatically generate test patterns for circuit fault detection based on the netlist and device model of the PCB. The PC should feature at least two boards with 32-bit I/O pins each, facilitating read and write operations. The test software comprises preprocessors and execution units. Preprocessors analyze test graphs to derive possible relationships, resulting in a set of files containing storage and control information. The execution unit loads these files to execute tests, involving reading stored information, inputting data to the appropriate ports, reading data from output ports, and comparing it with expected results. Fault detection triggers marking and location identification, supplemented by diagnostic programs for precise fault localization.
2.3 Test content
1) Testing the connectivity of the PCB’s I/O pins, crucial for providing access channels to the tester.
2) Verifying the integrity of IC chips on the PCB, assessing potential damage incurred during the chip assembly process via built-in self-tests and internal tests.
3) Identifying open circuit and short circuit faults in IC chip interconnections on the PCB, validated through external tests.
4) Assessing the integrity of the bus on the PCB to detect open circuit faults on the I/O pins of IC chips connected to the bus.
As BST technology advances, PCB testing continues to improve, benefiting from the widespread adoption of programmable integrated circuits. This enhances the flexibility and applicability of PCB testing while reducing associated test system costs. Designers can leverage programmable logic integrated circuits to create versatile PCBs
