PCB EMI Design Specification Steps

• IC Power Processing

  Ensure that each integrated circuit (IC) power PIN is equipped with a 0.1μF decoupling capacitor. For Ball Grid Array (BGA) chips, place eight capacitors (0.1μF and 0.01μF) at the four corners. Pay special attention to adding filter capacitors, such as VTT, for power supply traces. This not only affects stability but also has a significant impact on Electromagnetic Interference (EMI).

• Handling of the Clock Line

  When designing PCBs, it is recommended to prioritize routing the clock line first to optimize performance.

  • For Clock Lines with Frequencies of 66M or Higher:

    Limit the number of vias per line to 2, with an average not exceeding 1.5.

  • For Clock Lines with Frequencies Below 66M:

    Restrict the number of vias per line to 3, with an average not exceeding 2.5.

  • For Clock Lines Longer than 12 Inches:

    If the frequency exceeds 20M, ensure that the number of vias does not surpass 2.