As miniaturization continues to advance, PCB component and wiring technologies have also made significant progress. For example, highly integrated miniature ICs are now packaged in BGA housings, and the insulation spacing between conductors has been reduced to 0.5mm. The wiring design of electronic components plays a crucial role in ensuring successful testing during the production process.
To minimize costs associated with production tests, it is important to follow specific procedures, such as DFT (Design for Testability). These procedures, developed over the years, may need to be adapted as new production and component technologies emerge. As electronic products become smaller, challenges arise, including limited circuit nodes for contact and restrictions on methods like In-Circuit-Test Apps.
To address these challenges, adjustments can be made in circuit layout and new test methods can be adopted. Solutions may involve innovative adapter solutions or additional tasks for the test system, such as programming memory components or implementing integrated component self-tests (BIST). By integrating these steps into the test system, more value can be added.
To successfully implement these measures, careful considerations must be made during the product research and development stage.
1. What is testability
The concept of testability can be defined as the ability for test engineers to use simple methods to assess the characteristics of a specific component and determine if it meets the required functions. In simpler terms:
What is the simplicity of the method used to test if a product meets technical specifications?
How quickly can a test program be developed?
How thorough is the identification of product failures?
How easy is it to access test points?
In order to achieve effective testability, both mechanical and electrical design practices need to be taken into consideration. While there may be a cost associated with achieving testability, it offers a range of benefits for the overall production process and is therefore an essential requirement for successful product manufacturing.
2. Why develop test-friendly techniques
In the past, when a product couldn’t be tested at a certain point, the issue would often be passed on to another test point. If a product defect couldn’t be identified during production testing, the problem would simply be pushed to functional and system testing. However, in today’s context, there is a push to identify defects as early as possible. This approach not only reduces costs but is especially crucial given the complexity of modern products. Some manufacturing defects may go undetected during functional testing, especially in components requiring pre-installed software or programming (such as flash memory or ISPs). Planning for the programming of these components must be done during the development phase, and the test system must be equipped to handle this programming. Designing circuits with testability in mind may incur some costs, but dealing with challenging circuit designs can prove to be even more costly. Testing itself comes with a cost, and this cost escalates as testing progresses from online tests to functional tests and system tests. Skipping any of these tests would result in even higher costs, with a general rule of a tenfold increase in cost for each test skipped. With a test-friendly circuit design, faults can be caught early on, allowing the money spent on such a design to be quickly recouped.
3. How documentation impacts testability
A comprehensive understanding of component data is essential for developing a test program that can effectively identify faults. In many cases, close collaboration between development and testing teams is necessary. Documentation plays a crucial role in providing test engineers with the necessary information about component functionality and development test strategies. To overcome challenges arising from inadequate documentation or limited understanding of component functionality, test system manufacturers can rely on software tools to generate test patterns randomly or utilize non-vector methods as a temporary solution. Comprehensive documentation before testing includes a parts list, circuit design data (particularly CAD data), and detailed information about the functionality of service components (such as data sheets). With access to all relevant information, test vectors can be compiled, component failure patterns can be defined, or specific pre-adjustments can be made. Mechanical data is also important for checking components for proper soldering and alignment. For programmable components like flash memory, PLDs, and FPGAs, programming on the test system is necessary if not done during installation. The programming data for these components should be complete and accurately reflect the component’s specifications. Standard formats like Intel’s Hex or Motorola’s S-record structure should be used for programming data, as most test systems can interpret these formats for programming flash or ISP components. Much of the information mentioned is also critical for component fabrication. It is vital to differentiate between manufacturability and testability, as these are distinct concepts that require different considerations.
4. Mechanical contact conditions for optimal testability
Even circuits with excellent electrical testability can present challenges for testing without considering mechanical grounding principles. Several factors can impede electrical testability, such as insufficient or small test points that make it difficult for probe bed adapters to access all circuit nodes. Large errors in test point positioning or sizing can lead to poor test repeatability. When using probe bed adapters, it is crucial to follow recommendations regarding the size and positioning of latch holes and test points.
5. Electrical requirements for testability
Both mechanical contact conditions and electrical prerequisites are vital for achieving good testability. A gate circuit that cannot be tested poses a challenge, typically because the start input terminal cannot be accessed via a test point or is inaccessible from the package exterior. It is important to ensure that all components intended for online testing have mechanisms for electrical isolation. This can be achieved by disabling the input that controls the element’s output to maintain a static high-ohmic state. While most test systems can drive a node’s state to any level, the node involved should still be equipped with a disabled input, transitioning the node to a high-ohmic state before applying the corresponding level. The start input should never be directly connected to the circuit but through a 100-ohm resistor. Each component should have its own start, reset, or control pins to avoid a situation where multiple component start inputs share a resistor connected to the circuit. This principle applies to ASIC components as well, which should also have a lead pin to bring the output to a high-ohmic state. If a component can be reset when the operating voltage is applied, it is beneficial for the tester to initiate a reset prior to testing. Unused component leads should be accessible to prevent undiscovered shorts that could lead to component failure. Additionally, unused gates may be repurposed for design enhancements, underscoring the importance of testing these from the outset to ensure their reliability.
6. Flash memory and other programmable components
Programming flash memory can sometimes be time-consuming, especially for large memories or memory banks that may take up to a minute to program. During this time, back-driving other components is not recommended, as it could damage the flash memory. To prevent this, components connected to the address bus control lines must be set to a high-ohmic state. The data bus should also be switchable to enable unloading and reprogramming of the flash memory. In the case of in-system programmable components (ISPs) like those from Altera, Xilinx, and Lattice, specific requirements must be met in addition to mechanical and electrical prerequisites for testability. For Altera and Xilinx components, a Serial Vector Format (SVF) is commonly used for programming, while Lattice components require data in JEDEC format. After programming, the data is used to verify component functionality. The programming data provided by the development team should be easily compatible with the test system or require minimal transformation.
7. Considerations for boundary-scan (JTAG) testing
Complex circuits with dense components may pose challenges for test engineers in accessing test points. Boundary-scan and integrated self-test techniques offer solutions to enhance testability, reduce test completion time, and improve test accuracy. Implementing a test strategy based on boundary-scan and integrated self-test techniques may come at an added cost for development and test engineers. Using boundary-scan components based on the IEEE-1149.1 standard, developers should ensure specific test leads are accessible (e.g., TDI, TDO, TCK, TMS, and test reset) for effective boundary-scan testing. Developing a Boundary Scan Description Language (BSDL) model for components allows test engineers to leverage boundary-scan features and diagnostic capabilities. Boundary-scan testing can pinpoint shorts and opens down to the lead level and trigger automatic component testing with commands like “RunBIST.” When confronted with complex components lacking customary test models, using boundary-scan components can significantly reduce the formulation cost. The extent of time and cost savings varies depending on the element, with boundary-scan drastically reducing the number of test vectors required for fault detection compared to traditional testing methods. The decision to utilize boundary-scan testing should weigh the increased development and manufacturing costs against the benefits of faster fault identification, shorter test times, speed to market, adapter costs, and overall savings. In many scenarios, a hybrid approach combining traditional in-line testing methods with boundary-scan techniques proves to be the most effective solution on PCB boards.
To minimize costs associated with production tests, it is important to follow specific procedures, such as DFT (Design for Testability). These procedures, developed over the years, may need to be adapted as new production and component technologies emerge. As electronic products become smaller, challenges arise, including limited circuit nodes for contact and restrictions on methods like In-Circuit-Test Apps.
To address these challenges, adjustments can be made in circuit layout and new test methods can be adopted. Solutions may involve innovative adapter solutions or additional tasks for the test system, such as programming memory components or implementing integrated component self-tests (BIST). By integrating these steps into the test system, more value can be added.
To successfully implement these measures, careful considerations must be made during the product research and development stage.
1. What is testability
The concept of testability can be defined as the ability for test engineers to use simple methods to assess the characteristics of a specific component and determine if it meets the required functions. In simpler terms:
What is the simplicity of the method used to test if a product meets technical specifications?
How quickly can a test program be developed?
How thorough is the identification of product failures?
How easy is it to access test points?
In order to achieve effective testability, both mechanical and electrical design practices need to be taken into consideration. While there may be a cost associated with achieving testability, it offers a range of benefits for the overall production process and is therefore an essential requirement for successful product manufacturing.
2. Why develop test-friendly techniques
In the past, when a product couldn’t be tested at a certain point, the issue would often be passed on to another test point. If a product defect couldn’t be identified during production testing, the problem would simply be pushed to functional and system testing. However, in today’s context, there is a push to identify defects as early as possible. This approach not only reduces costs but is especially crucial given the complexity of modern products. Some manufacturing defects may go undetected during functional testing, especially in components requiring pre-installed software or programming (such as flash memory or ISPs). Planning for the programming of these components must be done during the development phase, and the test system must be equipped to handle this programming. Designing circuits with testability in mind may incur some costs, but dealing with challenging circuit designs can prove to be even more costly. Testing itself comes with a cost, and this cost escalates as testing progresses from online tests to functional tests and system tests. Skipping any of these tests would result in even higher costs, with a general rule of a tenfold increase in cost for each test skipped. With a test-friendly circuit design, faults can be caught early on, allowing the money spent on such a design to be quickly recouped.
3. How documentation impacts testability
A comprehensive understanding of component data is essential for developing a test program that can effectively identify faults. In many cases, close collaboration between development and testing teams is necessary. Documentation plays a crucial role in providing test engineers with the necessary information about component functionality and development test strategies. To overcome challenges arising from inadequate documentation or limited understanding of component functionality, test system manufacturers can rely on software tools to generate test patterns randomly or utilize non-vector methods as a temporary solution. Comprehensive documentation before testing includes a parts list, circuit design data (particularly CAD data), and detailed information about the functionality of service components (such as data sheets). With access to all relevant information, test vectors can be compiled, component failure patterns can be defined, or specific pre-adjustments can be made. Mechanical data is also important for checking components for proper soldering and alignment. For programmable components like flash memory, PLDs, and FPGAs, programming on the test system is necessary if not done during installation. The programming data for these components should be complete and accurately reflect the component’s specifications. Standard formats like Intel’s Hex or Motorola’s S-record structure should be used for programming data, as most test systems can interpret these formats for programming flash or ISP components. Much of the information mentioned is also critical for component fabrication. It is vital to differentiate between manufacturability and testability, as these are distinct concepts that require different considerations.
4. Mechanical contact conditions for optimal testability
Even circuits with excellent electrical testability can present challenges for testing without considering mechanical grounding principles. Several factors can impede electrical testability, such as insufficient or small test points that make it difficult for probe bed adapters to access all circuit nodes. Large errors in test point positioning or sizing can lead to poor test repeatability. When using probe bed adapters, it is crucial to follow recommendations regarding the size and positioning of latch holes and test points.
5. Electrical requirements for testability
Both mechanical contact conditions and electrical prerequisites are vital for achieving good testability. A gate circuit that cannot be tested poses a challenge, typically because the start input terminal cannot be accessed via a test point or is inaccessible from the package exterior. It is important to ensure that all components intended for online testing have mechanisms for electrical isolation. This can be achieved by disabling the input that controls the element’s output to maintain a static high-ohmic state. While most test systems can drive a node’s state to any level, the node involved should still be equipped with a disabled input, transitioning the node to a high-ohmic state before applying the corresponding level. The start input should never be directly connected to the circuit but through a 100-ohm resistor. Each component should have its own start, reset, or control pins to avoid a situation where multiple component start inputs share a resistor connected to the circuit. This principle applies to ASIC components as well, which should also have a lead pin to bring the output to a high-ohmic state. If a component can be reset when the operating voltage is applied, it is beneficial for the tester to initiate a reset prior to testing. Unused component leads should be accessible to prevent undiscovered shorts that could lead to component failure. Additionally, unused gates may be repurposed for design enhancements, underscoring the importance of testing these from the outset to ensure their reliability.
6. Flash memory and other programmable components
Programming flash memory can sometimes be time-consuming, especially for large memories or memory banks that may take up to a minute to program. During this time, back-driving other components is not recommended, as it could damage the flash memory. To prevent this, components connected to the address bus control lines must be set to a high-ohmic state. The data bus should also be switchable to enable unloading and reprogramming of the flash memory. In the case of in-system programmable components (ISPs) like those from Altera, Xilinx, and Lattice, specific requirements must be met in addition to mechanical and electrical prerequisites for testability. For Altera and Xilinx components, a Serial Vector Format (SVF) is commonly used for programming, while Lattice components require data in JEDEC format. After programming, the data is used to verify component functionality. The programming data provided by the development team should be easily compatible with the test system or require minimal transformation.
7. Considerations for boundary-scan (JTAG) testing
Complex circuits with dense components may pose challenges for test engineers in accessing test points. Boundary-scan and integrated self-test techniques offer solutions to enhance testability, reduce test completion time, and improve test accuracy. Implementing a test strategy based on boundary-scan and integrated self-test techniques may come at an added cost for development and test engineers. Using boundary-scan components based on the IEEE-1149.1 standard, developers should ensure specific test leads are accessible (e.g., TDI, TDO, TCK, TMS, and test reset) for effective boundary-scan testing. Developing a Boundary Scan Description Language (BSDL) model for components allows test engineers to leverage boundary-scan features and diagnostic capabilities. Boundary-scan testing can pinpoint shorts and opens down to the lead level and trigger automatic component testing with commands like “RunBIST.” When confronted with complex components lacking customary test models, using boundary-scan components can significantly reduce the formulation cost. The extent of time and cost savings varies depending on the element, with boundary-scan drastically reducing the number of test vectors required for fault detection compared to traditional testing methods. The decision to utilize boundary-scan testing should weigh the increased development and manufacturing costs against the benefits of faster fault identification, shorter test times, speed to market, adapter costs, and overall savings. In many scenarios, a hybrid approach combining traditional in-line testing methods with boundary-scan techniques proves to be the most effective solution on PCB boards.