The following is an introduction to PCB design guidelines aimed at ensuring signal integrity and resolving signal integrity (SI) issues:
(SI) Addressing problems early leads to higher design efficiency, preventing the need for terminal equipment additions before the PCB design is finalized.
Various tools and resources are available for SI design planning. This article focuses on core SI challenges and methods to address them, without delving into the technical specifics of the design process.
1. SI Problems: As IC output switching speeds increase, nearly all designs encounter signal integrity issues, regardless of the signal period.
The circuit board can be fully grounded, forming an easy power loop, and a large number of discrete terminal devices may be used as needed. However, the design must remain correct, avoiding any critical conditions. SI and EMC experts typically run simulations and calculations before routing, after which the board design follows strict design rules. If there are uncertainties, termination equipment may be added to maximize the SI safety margin. During the actual operation of the circuit board, some issues will inevitably arise. Therefore, using controlled impedance routing can help mitigate SI problems.
In summary, an ultra-standard design approach effectively addresses SI issues.
The following outlines common Signal Integrity (SI) design guidelines for the PCB design process.
2. **Pre-design Preparation**: Before beginning the design, the first step is to consider and establish the design strategy. This strategy will guide decisions related to component selection, process choices, and circuit board production cost control. For SI, conduct preliminary research to form a planning or design guideline that ensures the design does not present obvious SI issues, crosstalk, or timing problems. IC manufacturers often provide design guidelines, but these, or your own internal guidelines, have limitations. Following these guidelines alone may not result in a design that fully meets SI requirements.
If the design rules are simple, there may be no need for a dedicated PCB design engineer.
Before starting the actual PCB layout, there are several issues that must be addressed. These issues will typically affect the design of the circuit board. If there are a large number of circuit boards, resolving these problems early can add significant value.
3. **Cascaded Circuit Boards**: Some project teams have a high degree of autonomy in determining the number of PCB layers, while others may not. Therefore, understanding the specific project requirements is crucial. Communication with manufacturing and cost analysis engineers will help determine the cascade error of the circuit board, presenting an opportunity to identify the manufacturing tolerance of the board. This information is essential for the pre-routing phase. Based on these insights, you can decide how to arrange the cascading layers. It’s important to note that nearly every PCB inserted into another circuit board or backplane has specific thickness requirements. Most PCB manufacturers have fixed thickness limits for the types of layers they can produce, which significantly impacts the number of layers you can use. Close collaboration with the manufacturer is key to defining the number of cascades.
Impedance control tools should be utilized to define the target impedance ranges for different layers, considering the manufacturing tolerances provided by the manufacturer and the influence of adjacent routing. Ideally, for optimal signal integrity, high-speed nodes should be routed on controlled impedance inner layers (such as stripline). However, in practice, engineers often need to use the outer layers for all or part of these high-speed nodes. To optimize SI and maintain decoupling on the circuit board, ground and power planes should ideally be paired. If only one ground/power plane is available, it could lead to SI problems by definition.
Before defining the return path for undefined signals, you may encounter situations where simulating or predicting the performance of the circuit board is challenging.
4. **Crosstalk and Impedance Control**: Coupling between adjacent signal lines can cause crosstalk and alter the impedance of the signal line. Analyzing the coupling between adjacent parallel signal lines can help determine the “safe” spacing or the minimum parallel wiring length required between signal lines. For example, to limit crosstalk between clock and data signals to 100mV while maintaining parallel routing, you can calculate or simulate the minimum allowable spacing between the signals on a given layer. Additionally, if the design includes nodes that are sensitive to impedance (such as clocks or high-speed memory interfaces), routing must be carefully managed to achieve the desired impedance on one or more layers.
5. **Key High-speed Node Delays and Timing**: Delays and timing at high-speed nodes are critical, especially for clock routing. Due to stringent timing requirements, nodes typically need to use specialized terminal equipment to achieve the best SI performance. Identifying these nodes early in the design process and allocating time for adjusting component placement and routing is crucial for optimizing signal integrity.
6. **Choice of PCB Technology and Drive Technology**: Different tasks require different types of drive technologies. Are signals routed point-to-point or through multiple paths? Does the signal need to be output from the board, or can it remain on the same board? What are the allowable time delays and noise tolerance? As a general rule for SI design, the slower the signal rise time, the better the signal integrity. For example, there is no reason for a 50MHz clock to have a 500ps rise time. A 2-3ns swing frequency control device is fast enough to ensure good SI quality and help mitigate issues related to simultaneous switching output (SSO) and electromagnetic compatibility (EMC). With new FPGA programmable technologies or custom ASIC designs, there is greater flexibility in adjusting drive amplitude and speed.
At the beginning of the design process, meet the FPGA (or ASIC) timing requirements and select appropriate output options, including pin assignments, if possible. At this stage, it’s important to obtain a suitable simulation model from the IC supplier. To effectively cover SI simulation, you will need a SI simulator and a corresponding simulation model, likely an IBIS model.
Finally, in the pre-routing stage, it’s important to establish a series of design guidelines, including target layer impedance, routing spacing, preferred device technologies, key node topologies, and termination strategies.
7. **Pre-wiring Process**: In the pre-wiring stage, the first step is to define the input parameters for SI analysis, including drive amplitude, impedance, and tracking speed, along with potential topological constraints (e.g., minimum/maximum length, short lengths). Afterward, simulate and analyze the timing and SI results to find an acceptable range of values. This range can then be interpreted as wiring constraints for the PCB layout. Various software tools can help with this “cleanup” preparation, allowing automatic handling of these constraints during the routing process.
Post-wiring SI simulations are useful for verifying the design and ensuring that the design rules are followed. However, this step is typically only necessary for cost-sensitive designs or projects with strict routing requirements.
9. **Ensuring SI Quality**: Once the circuit board is assembled, it should be placed on a test platform and measured using tools like an oscilloscope or Time Domain Reflectometer (TDR). Compare the actual performance of the PCB with the expected simulation results. Many articles cover model selection, and engineers performing static timing verification often notice that while device data sheets provide necessary data, building accurate models can still be challenging. Compared to SI simulation models, creating the models themselves is relatively straightforward, but obtaining the necessary model data is often difficult. The only reliable source of SI model data is the IC supplier, making collaboration with them critical. The IBIS model standard provides a consistent data format, but developing and maintaining the IBIS model comes with significant costs. IC suppliers must be motivated by market demand to invest in this process, and the PCB manufacturer may be the only party to push for these improvements in the market.
(SI) Addressing problems early leads to higher design efficiency, preventing the need for terminal equipment additions before the PCB design is finalized.
Various tools and resources are available for SI design planning. This article focuses on core SI challenges and methods to address them, without delving into the technical specifics of the design process.
1. SI Problems: As IC output switching speeds increase, nearly all designs encounter signal integrity issues, regardless of the signal period.
The circuit board can be fully grounded, forming an easy power loop, and a large number of discrete terminal devices may be used as needed. However, the design must remain correct, avoiding any critical conditions. SI and EMC experts typically run simulations and calculations before routing, after which the board design follows strict design rules. If there are uncertainties, termination equipment may be added to maximize the SI safety margin. During the actual operation of the circuit board, some issues will inevitably arise. Therefore, using controlled impedance routing can help mitigate SI problems.
In summary, an ultra-standard design approach effectively addresses SI issues.
The following outlines common Signal Integrity (SI) design guidelines for the PCB design process.
2. **Pre-design Preparation**: Before beginning the design, the first step is to consider and establish the design strategy. This strategy will guide decisions related to component selection, process choices, and circuit board production cost control. For SI, conduct preliminary research to form a planning or design guideline that ensures the design does not present obvious SI issues, crosstalk, or timing problems. IC manufacturers often provide design guidelines, but these, or your own internal guidelines, have limitations. Following these guidelines alone may not result in a design that fully meets SI requirements.
If the design rules are simple, there may be no need for a dedicated PCB design engineer.
Before starting the actual PCB layout, there are several issues that must be addressed. These issues will typically affect the design of the circuit board. If there are a large number of circuit boards, resolving these problems early can add significant value.
3. **Cascaded Circuit Boards**: Some project teams have a high degree of autonomy in determining the number of PCB layers, while others may not. Therefore, understanding the specific project requirements is crucial. Communication with manufacturing and cost analysis engineers will help determine the cascade error of the circuit board, presenting an opportunity to identify the manufacturing tolerance of the board. This information is essential for the pre-routing phase. Based on these insights, you can decide how to arrange the cascading layers. It’s important to note that nearly every PCB inserted into another circuit board or backplane has specific thickness requirements. Most PCB manufacturers have fixed thickness limits for the types of layers they can produce, which significantly impacts the number of layers you can use. Close collaboration with the manufacturer is key to defining the number of cascades.
Impedance control tools should be utilized to define the target impedance ranges for different layers, considering the manufacturing tolerances provided by the manufacturer and the influence of adjacent routing. Ideally, for optimal signal integrity, high-speed nodes should be routed on controlled impedance inner layers (such as stripline). However, in practice, engineers often need to use the outer layers for all or part of these high-speed nodes. To optimize SI and maintain decoupling on the circuit board, ground and power planes should ideally be paired. If only one ground/power plane is available, it could lead to SI problems by definition.
Before defining the return path for undefined signals, you may encounter situations where simulating or predicting the performance of the circuit board is challenging.
4. **Crosstalk and Impedance Control**: Coupling between adjacent signal lines can cause crosstalk and alter the impedance of the signal line. Analyzing the coupling between adjacent parallel signal lines can help determine the “safe” spacing or the minimum parallel wiring length required between signal lines. For example, to limit crosstalk between clock and data signals to 100mV while maintaining parallel routing, you can calculate or simulate the minimum allowable spacing between the signals on a given layer. Additionally, if the design includes nodes that are sensitive to impedance (such as clocks or high-speed memory interfaces), routing must be carefully managed to achieve the desired impedance on one or more layers.
5. **Key High-speed Node Delays and Timing**: Delays and timing at high-speed nodes are critical, especially for clock routing. Due to stringent timing requirements, nodes typically need to use specialized terminal equipment to achieve the best SI performance. Identifying these nodes early in the design process and allocating time for adjusting component placement and routing is crucial for optimizing signal integrity.
6. **Choice of PCB Technology and Drive Technology**: Different tasks require different types of drive technologies. Are signals routed point-to-point or through multiple paths? Does the signal need to be output from the board, or can it remain on the same board? What are the allowable time delays and noise tolerance? As a general rule for SI design, the slower the signal rise time, the better the signal integrity. For example, there is no reason for a 50MHz clock to have a 500ps rise time. A 2-3ns swing frequency control device is fast enough to ensure good SI quality and help mitigate issues related to simultaneous switching output (SSO) and electromagnetic compatibility (EMC). With new FPGA programmable technologies or custom ASIC designs, there is greater flexibility in adjusting drive amplitude and speed.
At the beginning of the design process, meet the FPGA (or ASIC) timing requirements and select appropriate output options, including pin assignments, if possible. At this stage, it’s important to obtain a suitable simulation model from the IC supplier. To effectively cover SI simulation, you will need a SI simulator and a corresponding simulation model, likely an IBIS model.
Finally, in the pre-routing stage, it’s important to establish a series of design guidelines, including target layer impedance, routing spacing, preferred device technologies, key node topologies, and termination strategies.
7. **Pre-wiring Process**: In the pre-wiring stage, the first step is to define the input parameters for SI analysis, including drive amplitude, impedance, and tracking speed, along with potential topological constraints (e.g., minimum/maximum length, short lengths). Afterward, simulate and analyze the timing and SI results to find an acceptable range of values. This range can then be interpreted as wiring constraints for the PCB layout. Various software tools can help with this “cleanup” preparation, allowing automatic handling of these constraints during the routing process.
Post-wiring SI simulations are useful for verifying the design and ensuring that the design rules are followed. However, this step is typically only necessary for cost-sensitive designs or projects with strict routing requirements.
9. **Ensuring SI Quality**: Once the circuit board is assembled, it should be placed on a test platform and measured using tools like an oscilloscope or Time Domain Reflectometer (TDR). Compare the actual performance of the PCB with the expected simulation results. Many articles cover model selection, and engineers performing static timing verification often notice that while device data sheets provide necessary data, building accurate models can still be challenging. Compared to SI simulation models, creating the models themselves is relatively straightforward, but obtaining the necessary model data is often difficult. The only reliable source of SI model data is the IC supplier, making collaboration with them critical. The IBIS model standard provides a consistent data format, but developing and maintaining the IBIS model comes with significant costs. IC suppliers must be motivated by market demand to invest in this process, and the PCB manufacturer may be the only party to push for these improvements in the market.
