1. PCB Parallel Termination
2. PCB parallel termination is primarily used to add pull-up and/or pull-down impedance as close as possible to the load end to achieve impedance matching at the terminal. Depending on different application environments, PCB parallel termination can be categorized into the following types:
3. (I) Simple PCB Parallel Termination. This termination method involves adding a resistor RT (RT=Z0) connected to the GROUND at the load end to achieve impedance matching. The requirement for using this termination method is that the drive end must be capable of providing the necessary drive current when the output is high to ensure that the high-level voltage across the termination resistor meets the threshold voltage requirement. When the output is in a high-level state,
1. This PCB parallel termination circuit consumes too much current. For a 50Ω termination load, maintaining a high TTL level consumes up to 48mA. Consequently, it is challenging for general devices to reliably support this type of termination.
2. **Connect the circuit** (II) Thevenin PCB parallel termination is a voltage divider type termination. It uses a pull-up resistor R1 and a pull-down resistor R2 to form a termination resistor and absorbs reflections through R1 and R2. The resistance values for R1 and R2 are determined by the following conditions: The maximum value of R1 is based on the maximum rise time of the acceptable signal (which is a function of the RC charge and discharge time constant), and the minimum value of R1 is determined by the current sink capability of the drive source. The choice of R2 should meet the logic high level requirement of the circuit when the transmission line is disconnected. Thevenin equivalent impedance can be expressed as: RT is required to be equal to the transmission line impedance Z0 for optimal matching. Although this termination scheme reduces the drive capability requirements for the source-side devices, the resistance R1 and R2 connected between VCC and GROUND continuously draw current from the system power supply, resulting in relatively high DC power consumption.
3. **Active PCB parallel termination** In this strategy, the termination resistor RT (RT=Z0) pulls the load terminal signal to an offset voltage VBIAS. The selection of VBIAS is based on ensuring the output drive source can handle current for high and low-level signals. This type of termination requires an independent voltage source capable of sourcing and sinking current to meet the jump speed requirements of the output voltage. In this scheme, if the offset voltage VBIAS is positive and the input is at a logic low level, DC power loss occurs. Conversely, if VBIAS is a negative voltage, DC power loss occurs when the input is at a logic high level.
4. **PCB parallel AC termination** The PCB parallel AC termination employs a resistor and capacitor network (series RC) as the termination impedance. The termination resistance R must be less than or equal to the transmission line impedance Z0, and the capacitance C must be greater than 100pF, with 0.1µF multilayer ceramic capacitors recommended. The capacitor blocks low and high frequencies, so the resistance R does not act as a DC load on the driving source, resulting in no DC power consumption.
2. PCB parallel termination is primarily used to add pull-up and/or pull-down impedance as close as possible to the load end to achieve impedance matching at the terminal. Depending on different application environments, PCB parallel termination can be categorized into the following types:
3. (I) Simple PCB Parallel Termination. This termination method involves adding a resistor RT (RT=Z0) connected to the GROUND at the load end to achieve impedance matching. The requirement for using this termination method is that the drive end must be capable of providing the necessary drive current when the output is high to ensure that the high-level voltage across the termination resistor meets the threshold voltage requirement. When the output is in a high-level state,
1. This PCB parallel termination circuit consumes too much current. For a 50Ω termination load, maintaining a high TTL level consumes up to 48mA. Consequently, it is challenging for general devices to reliably support this type of termination.
2. **Connect the circuit** (II) Thevenin PCB parallel termination is a voltage divider type termination. It uses a pull-up resistor R1 and a pull-down resistor R2 to form a termination resistor and absorbs reflections through R1 and R2. The resistance values for R1 and R2 are determined by the following conditions: The maximum value of R1 is based on the maximum rise time of the acceptable signal (which is a function of the RC charge and discharge time constant), and the minimum value of R1 is determined by the current sink capability of the drive source. The choice of R2 should meet the logic high level requirement of the circuit when the transmission line is disconnected. Thevenin equivalent impedance can be expressed as: RT is required to be equal to the transmission line impedance Z0 for optimal matching. Although this termination scheme reduces the drive capability requirements for the source-side devices, the resistance R1 and R2 connected between VCC and GROUND continuously draw current from the system power supply, resulting in relatively high DC power consumption.
3. **Active PCB parallel termination** In this strategy, the termination resistor RT (RT=Z0) pulls the load terminal signal to an offset voltage VBIAS. The selection of VBIAS is based on ensuring the output drive source can handle current for high and low-level signals. This type of termination requires an independent voltage source capable of sourcing and sinking current to meet the jump speed requirements of the output voltage. In this scheme, if the offset voltage VBIAS is positive and the input is at a logic low level, DC power loss occurs. Conversely, if VBIAS is a negative voltage, DC power loss occurs when the input is at a logic high level.
4. **PCB parallel AC termination** The PCB parallel AC termination employs a resistor and capacitor network (series RC) as the termination impedance. The termination resistance R must be less than or equal to the transmission line impedance Z0, and the capacitance C must be greater than 100pF, with 0.1µF multilayer ceramic capacitors recommended. The capacitor blocks low and high frequencies, so the resistance R does not act as a DC load on the driving source, resulting in no DC power consumption.
