Vias are crucial components in multi-layer PCB boards, with drilling costs typically comprising 30% to 40% of PCB production expenses. Simply put, any hole on a PCB can be classified as a via.
1. Functionally, vias can be categorized as follows:
1) Electrical connection between layers;
2) Fixing or positioning devices.
In terms of process, vias are typically classified into three types: blind vias, buried vias, and through vias.
Blind vias exist on the top and bottom surfaces of the PCB, reaching a certain depth to link surface and inner circuits. The depth of these holes usually does not exceed a specific ratio to their diameter.
Buried vias are connection holes within PCB layers that do not extend to the surface. Both types are located within the inner layers and are formed before lamination, allowing them to overlap multiple inner layers.
Through-holes penetrate the entire PCB and can serve as internal connections or component mounting locations. Because they are easier to implement and more cost-effective, most PCBs utilize through-holes rather than blind or buried vias unless specified otherwise.
Design-wise, a via typically consists of a drill hole at its center and a pad area surrounding it. The dimensions of these components determine the overall size of the via. Designers of high-speed, high-density PCBs favor smaller vias to maximize wiring space and reduce parasitic capacitance, making them ideal for high-speed circuits. However, shrinking the hole size increases costs and is limited by drilling and plating processes. Smaller holes require longer drilling times, are more prone to off-center deviations, and face difficulties in uniform copper plating if the hole depth exceeds 6 times its diameter. For instance, a standard 6-layer PCB typically has a thickness of about 50 mils, limiting the manufacturer’s hole diameter to 8 mils.
2. Parasitic capacitance of vias
The vias themselves have parasitic capacitances to the ground. If it is known that the diameter of the isolation holes of the vias on the ground layer is D2, the diameter of the via pads is D1, and the thickness of the PCB board is T, The dielectric constant of the board substrate is ε, then the parasitic capacitance of the via is similar to:
C=1.41εTD1/(D2-D1)
The main impact of the parasitic capacitance of the via on the circuit is to prolong the rise time of the signal and reduce the speed of the circuit.
For example, for a PCB board with a thickness of 50Mil, if a via hole with an inner diameter of 10Mil and a pad diameter of 20Mil is used, and the distance between the pad and the ground copper area is 32Mil, we can approximate the via hole through the above formula. The parasitic capacitance is rough:
C=1.41×4.4×0.050×0.020/(0.032-0.020)=0.517pF,
The rise time change caused by this part of the capacitance is:
T10-90=2.2C(Z0/2)=2.2×0.517x(55/2)=31.28ps.
From these values, it can be seen that although the effect of the rise and delay caused by the parasitic capacitance of a single via is not very obvious, if the via is used multiple times in the trace to switch between layers, the designer should still consider carefully.
3. Parasitic inductance of vias
Similarly, there are parasitic inductances along with parasitic capacitances of vias. In the design of high-speed digital circuits, the harm caused by parasitic inductances of vias is often greater than the influence of parasitic capacitances. Its parasitic series inductance will weaken the contribution of the bypass capacitor and reduce the filtering effect of the entire power system.
We can easily calculate the approximate parasitic inductance of a via with the following formula: L=5.08h[ln(4h/d)+1] where L is the inductance of the via, h is the length of the via, and d is the diameter of the center drilled hole. It can be seen from the formula that the diameter of the via hole has little effect on the inductance, while the length of the via hole affects the inductance. Still using the above example, the inductance of the via can be calculated as: L=5.08×0.050[ln(4×0.050/0.010)+1]=1.015nH. If the rise time of the signal is 1ns, then its equivalent impedance is XL=πL/T10-90=3.19Ω. Such impedance can no longer be ignored when high-frequency current passes through.
It should be noted that the bypass capacitor needs to pass through two vias when connecting the power supply layer and the ground layer so that the parasitic inductance of the vias will be multiplied.
4. Via design in high-speed PCB board
Through the above analysis of the parasitic characteristics of vias, we can see that in the design of high-speed PCB boards, seemingly simple vias often bring a lot to the circuit design negative effects. In order to reduce the adverse effects caused by the parasitic effects of vias, you can try to do as much as possible in the design:
1) Considering both cost and signal quality, select a via the size of a reasonable size. For example, for 6-10 layer memory module PCB board design, it is better to use 10/20Mil (drilling/pad) vias. For some high-density small-sized boards, you can also try to use 8/18Mil. vias. Under the current technical conditions, it is difficult to use smaller vias. For power or ground vias, consider using larger sizes to reduce impedance.
2) From the two formulas discussed above, it can be concluded that using a thinner PCB board is beneficial to reduce the two parasitic parameters of the via.
3) Try not to change the layers of the signal traces on the PCB, that is to say, try not to use unnecessary vias.
4) The pins of the power supply and ground should be drilled as close as possible. The shorter the lead between the via and the pin, the better because they will increase the inductance. At the same time, the leads of power and ground should be as thick as possible to reduce impedance.
5) Place some grounded vias near the vias where the signal changes layers to provide a short return path for the signal. It is even possible to place a few redundant ground vias on the PCB in large numbers. Of course, flexibility is also required in the design. The via model discussed earlier in the case where each layer has pads, and sometimes, we can reduce or even remove the pads of some layers. Especially in the case of a very high density of vias, it may lead to the formation of a circuit breaker on the copper layer. To resolve this problem, in addition to moving the position of the via, we can also consider reducing the pad size on the PCB board.
1. Functionally, vias can be categorized as follows:
1) Electrical connection between layers;
2) Fixing or positioning devices.
In terms of process, vias are typically classified into three types: blind vias, buried vias, and through vias.
Blind vias exist on the top and bottom surfaces of the PCB, reaching a certain depth to link surface and inner circuits. The depth of these holes usually does not exceed a specific ratio to their diameter.
Buried vias are connection holes within PCB layers that do not extend to the surface. Both types are located within the inner layers and are formed before lamination, allowing them to overlap multiple inner layers.
Through-holes penetrate the entire PCB and can serve as internal connections or component mounting locations. Because they are easier to implement and more cost-effective, most PCBs utilize through-holes rather than blind or buried vias unless specified otherwise.
Design-wise, a via typically consists of a drill hole at its center and a pad area surrounding it. The dimensions of these components determine the overall size of the via. Designers of high-speed, high-density PCBs favor smaller vias to maximize wiring space and reduce parasitic capacitance, making them ideal for high-speed circuits. However, shrinking the hole size increases costs and is limited by drilling and plating processes. Smaller holes require longer drilling times, are more prone to off-center deviations, and face difficulties in uniform copper plating if the hole depth exceeds 6 times its diameter. For instance, a standard 6-layer PCB typically has a thickness of about 50 mils, limiting the manufacturer’s hole diameter to 8 mils.
2. Parasitic capacitance of vias
The vias themselves have parasitic capacitances to the ground. If it is known that the diameter of the isolation holes of the vias on the ground layer is D2, the diameter of the via pads is D1, and the thickness of the PCB board is T, The dielectric constant of the board substrate is ε, then the parasitic capacitance of the via is similar to:
C=1.41εTD1/(D2-D1)
The main impact of the parasitic capacitance of the via on the circuit is to prolong the rise time of the signal and reduce the speed of the circuit.
For example, for a PCB board with a thickness of 50Mil, if a via hole with an inner diameter of 10Mil and a pad diameter of 20Mil is used, and the distance between the pad and the ground copper area is 32Mil, we can approximate the via hole through the above formula. The parasitic capacitance is rough:
C=1.41×4.4×0.050×0.020/(0.032-0.020)=0.517pF,
The rise time change caused by this part of the capacitance is:
T10-90=2.2C(Z0/2)=2.2×0.517x(55/2)=31.28ps.
From these values, it can be seen that although the effect of the rise and delay caused by the parasitic capacitance of a single via is not very obvious, if the via is used multiple times in the trace to switch between layers, the designer should still consider carefully.
3. Parasitic inductance of vias
Similarly, there are parasitic inductances along with parasitic capacitances of vias. In the design of high-speed digital circuits, the harm caused by parasitic inductances of vias is often greater than the influence of parasitic capacitances. Its parasitic series inductance will weaken the contribution of the bypass capacitor and reduce the filtering effect of the entire power system.
We can easily calculate the approximate parasitic inductance of a via with the following formula: L=5.08h[ln(4h/d)+1] where L is the inductance of the via, h is the length of the via, and d is the diameter of the center drilled hole. It can be seen from the formula that the diameter of the via hole has little effect on the inductance, while the length of the via hole affects the inductance. Still using the above example, the inductance of the via can be calculated as: L=5.08×0.050[ln(4×0.050/0.010)+1]=1.015nH. If the rise time of the signal is 1ns, then its equivalent impedance is XL=πL/T10-90=3.19Ω. Such impedance can no longer be ignored when high-frequency current passes through.
It should be noted that the bypass capacitor needs to pass through two vias when connecting the power supply layer and the ground layer so that the parasitic inductance of the vias will be multiplied.
4. Via design in high-speed PCB board
Through the above analysis of the parasitic characteristics of vias, we can see that in the design of high-speed PCB boards, seemingly simple vias often bring a lot to the circuit design negative effects. In order to reduce the adverse effects caused by the parasitic effects of vias, you can try to do as much as possible in the design:
1) Considering both cost and signal quality, select a via the size of a reasonable size. For example, for 6-10 layer memory module PCB board design, it is better to use 10/20Mil (drilling/pad) vias. For some high-density small-sized boards, you can also try to use 8/18Mil. vias. Under the current technical conditions, it is difficult to use smaller vias. For power or ground vias, consider using larger sizes to reduce impedance.
2) From the two formulas discussed above, it can be concluded that using a thinner PCB board is beneficial to reduce the two parasitic parameters of the via.
3) Try not to change the layers of the signal traces on the PCB, that is to say, try not to use unnecessary vias.
4) The pins of the power supply and ground should be drilled as close as possible. The shorter the lead between the via and the pin, the better because they will increase the inductance. At the same time, the leads of power and ground should be as thick as possible to reduce impedance.
5) Place some grounded vias near the vias where the signal changes layers to provide a short return path for the signal. It is even possible to place a few redundant ground vias on the PCB in large numbers. Of course, flexibility is also required in the design. The via model discussed earlier in the case where each layer has pads, and sometimes, we can reduce or even remove the pads of some layers. Especially in the case of a very high density of vias, it may lead to the formation of a circuit breaker on the copper layer. To resolve this problem, in addition to moving the position of the via, we can also consider reducing the pad size on the PCB board.