As circuit board designs grow increasingly complex, they challenge the capabilities of existing hardware and power management architectures. Currently, there are four predominant circuit board management architectures. While all can accommodate these intricate designs, they inevitably require trade-offs in design scalability, workload, or cost.
Recently, a fifth type of circuit board management architecture has emerged, offering the ultimate performance, safety, and flexibility while significantly reducing design workload and construction costs. This article will explore this new architecture, emphasizing the power management functionalities it delivers.
Overview
We typically categorize a circuit board into two functional modules (Figure 1): load management (Payload Management) and hardware management (Hardware Management). For most circuit boards, the load function occupies 80% to 90% of the total PCB area (data/control layer and/or processor). The remaining 10% to 20% is dedicated to hardware management, responsible for hardware-level monitoring, control, or housekeeping.
Until recently, a novel decentralized architecture has emerged, offering greater scalability than its counterparts while also being implementable at a lower BOM cost. To clarify the benefits of the distributed architecture, we will first examine how to establish the power management function within the four most commonly used hardware management architectures (Figures 2-5), before further delving into the distributed architecture.
**Comparison of Power Management Architecture Based on Control PLD**
CPLD-based power management integrates power management functions into the on-board control PLD (CPLD). The CPLD monitors input power and the ‘Power Good’ signal from each DC-DC converter. It implements a timing algorithm to generate the ‘Enable’ signal for powering the load circuit, preventing damage or logic errors. The CPLD can also produce logic signals like Reset and Power Good, ensuring load components operate when power is applied or cease when power is removed. Additionally, it generates sequences to safely disable the power supply in case of a power failure or fault detection. PLDs effectively support event-driven solutions, providing tailored responses to various failure combinations.
**CPLD-Based Hardware Management System for Power Management and Housekeeping Functions**
In this design approach, all power sequencing, protection, and control functions are implemented using CPLD, typically coded in VHDL or Verilog.
**Advantages:**
– Low cost
– Intuitive architecture allows easy adjustment of timing logic for new applications
– Utilizes a design environment (commonly Verilog) for implementation
– Event-oriented architecture can flexibly respond to diverse failures
**Shortcomings:**
– Each power supply requires two signal channels, making larger, more complex designs challenge the CPLD I/O ports and circuit board congestion
– Power Good detection accuracy is limited (typically 8% to 20% error rate), hampering reliable power supply voltage monitoring
– Incorporating an automatic measurement function necessitates an A/D converter, increasing cost and complexity
– Requires a board-level engineer with digital circuit experience, often lacking expertise in power supply design
**Using Power Management IC for Power Management and CPLD for Housekeeping**
In this functionally split architecture, a power management IC oversees monitoring and sequencing of the circuit board’s DC-DC converters. As it directly monitors power supply voltage, it can perform fine-tuning and margining functions. The CPLD utilizes the power supply’s Power Good state to generate essential control, state, and housekeeping signals.
Designs often employ GUI-based configuration tools for power management IC functions, while CPLD logic is defined in VHDL or Verilog.
**Advantages:**
– Reduces CPLD I/O count, as the power management IC can handle the ‘Enable’ function
– Frees up board space, allowing for simpler layouts and fewer PCB layers
– Direct monitoring of power supply voltage by the power management IC provides more accurate overall system health information, enhancing stability
**Shortcomings:**
– Power management IC increases BOM cost, particularly when multiple components are needed
– While the architecture supports event-driven responses, deploying multiple power management ICs can heighten design complexity
– Adjusting sequences in complex designs becomes challenging, especially when distributing functions across several power management ICs
– The design process requires multiple tools (GUI + VHDL/Verilog), potentially necessitating more engineers and increasing design risk
**Using CPLD for Housekeeping and PMBus for MCU-Based Power Management Functions**
This architecture employs a microcontroller (MCU) to manage the power sequence of the digitally controlled point of load (DPOL). The MCU utilizes the power management bus (PMBus), a two-wire communication protocol based on the I2C bus, to oversee DPOL. The CPLD handles on-board housekeeping functions and controls any point-of-load DC-DC converter with an analog control interface (APOL). Most MCU-based power management designs adopt time-series schemes to streamline software design.
A potential drawback of software-based power management is longer fault response times (typically 10 to 15 milliseconds, while CPLD response times are in microseconds). For faults needing quicker responses or event-oriented sequences, a CPLD may be added as a secondary protective measure. Implementing software-based power management requires VHDL or Verilog for both MCU software and CPLD design.
**Advantages:**
– Easy to adjust designs (only for time-based sequences)
– A wealth of software development tools accelerates MCU-based solution debugging
– Firmware upgrades facilitate quick design changes
– PCB design is simplified, with excess wiring around DPOL
**Shortcomings:**
– Higher BOM costs
– Adjusting designs for event-driven sequence requirements is challenging
– Requires multiple design tools (Verilog/VHDL + software)
**Summary**
As PCB-level system designs grow increasingly complex, hardware management systems comprise a larger share of both design workload and BOM cost. Employing CPLD and POL power supplies for some or all management functions can alleviate challenges posed by these trends, though cost remains a barrier. Currently, distributed hardware management architectures are available, allowing CPLDs to connect to low-cost sensing components via a 3-wire serial link. This approach not only reduces design complexity, PCB space requirements, and BOM costs but also enables the use of various tools from analog and digital engineers.
Recently, a fifth type of circuit board management architecture has emerged, offering the ultimate performance, safety, and flexibility while significantly reducing design workload and construction costs. This article will explore this new architecture, emphasizing the power management functionalities it delivers.
Overview
We typically categorize a circuit board into two functional modules (Figure 1): load management (Payload Management) and hardware management (Hardware Management). For most circuit boards, the load function occupies 80% to 90% of the total PCB area (data/control layer and/or processor). The remaining 10% to 20% is dedicated to hardware management, responsible for hardware-level monitoring, control, or housekeeping.
Until recently, a novel decentralized architecture has emerged, offering greater scalability than its counterparts while also being implementable at a lower BOM cost. To clarify the benefits of the distributed architecture, we will first examine how to establish the power management function within the four most commonly used hardware management architectures (Figures 2-5), before further delving into the distributed architecture.
**Comparison of Power Management Architecture Based on Control PLD**
CPLD-based power management integrates power management functions into the on-board control PLD (CPLD). The CPLD monitors input power and the ‘Power Good’ signal from each DC-DC converter. It implements a timing algorithm to generate the ‘Enable’ signal for powering the load circuit, preventing damage or logic errors. The CPLD can also produce logic signals like Reset and Power Good, ensuring load components operate when power is applied or cease when power is removed. Additionally, it generates sequences to safely disable the power supply in case of a power failure or fault detection. PLDs effectively support event-driven solutions, providing tailored responses to various failure combinations.
**CPLD-Based Hardware Management System for Power Management and Housekeeping Functions**
In this design approach, all power sequencing, protection, and control functions are implemented using CPLD, typically coded in VHDL or Verilog.
**Advantages:**
– Low cost
– Intuitive architecture allows easy adjustment of timing logic for new applications
– Utilizes a design environment (commonly Verilog) for implementation
– Event-oriented architecture can flexibly respond to diverse failures
**Shortcomings:**
– Each power supply requires two signal channels, making larger, more complex designs challenge the CPLD I/O ports and circuit board congestion
– Power Good detection accuracy is limited (typically 8% to 20% error rate), hampering reliable power supply voltage monitoring
– Incorporating an automatic measurement function necessitates an A/D converter, increasing cost and complexity
– Requires a board-level engineer with digital circuit experience, often lacking expertise in power supply design
**Using Power Management IC for Power Management and CPLD for Housekeeping**
In this functionally split architecture, a power management IC oversees monitoring and sequencing of the circuit board’s DC-DC converters. As it directly monitors power supply voltage, it can perform fine-tuning and margining functions. The CPLD utilizes the power supply’s Power Good state to generate essential control, state, and housekeeping signals.
Designs often employ GUI-based configuration tools for power management IC functions, while CPLD logic is defined in VHDL or Verilog.
**Advantages:**
– Reduces CPLD I/O count, as the power management IC can handle the ‘Enable’ function
– Frees up board space, allowing for simpler layouts and fewer PCB layers
– Direct monitoring of power supply voltage by the power management IC provides more accurate overall system health information, enhancing stability
**Shortcomings:**
– Power management IC increases BOM cost, particularly when multiple components are needed
– While the architecture supports event-driven responses, deploying multiple power management ICs can heighten design complexity
– Adjusting sequences in complex designs becomes challenging, especially when distributing functions across several power management ICs
– The design process requires multiple tools (GUI + VHDL/Verilog), potentially necessitating more engineers and increasing design risk
**Using CPLD for Housekeeping and PMBus for MCU-Based Power Management Functions**
This architecture employs a microcontroller (MCU) to manage the power sequence of the digitally controlled point of load (DPOL). The MCU utilizes the power management bus (PMBus), a two-wire communication protocol based on the I2C bus, to oversee DPOL. The CPLD handles on-board housekeeping functions and controls any point-of-load DC-DC converter with an analog control interface (APOL). Most MCU-based power management designs adopt time-series schemes to streamline software design.
A potential drawback of software-based power management is longer fault response times (typically 10 to 15 milliseconds, while CPLD response times are in microseconds). For faults needing quicker responses or event-oriented sequences, a CPLD may be added as a secondary protective measure. Implementing software-based power management requires VHDL or Verilog for both MCU software and CPLD design.
**Advantages:**
– Easy to adjust designs (only for time-based sequences)
– A wealth of software development tools accelerates MCU-based solution debugging
– Firmware upgrades facilitate quick design changes
– PCB design is simplified, with excess wiring around DPOL
**Shortcomings:**
– Higher BOM costs
– Adjusting designs for event-driven sequence requirements is challenging
– Requires multiple design tools (Verilog/VHDL + software)
**Summary**
As PCB-level system designs grow increasingly complex, hardware management systems comprise a larger share of both design workload and BOM cost. Employing CPLD and POL power supplies for some or all management functions can alleviate challenges posed by these trends, though cost remains a barrier. Currently, distributed hardware management architectures are available, allowing CPLDs to connect to low-cost sensing components via a 3-wire serial link. This approach not only reduces design complexity, PCB space requirements, and BOM costs but also enables the use of various tools from analog and digital engineers.
