Power Line Layout in PCB Design

1. **Power Cord Layout**:

1. Based on the current requirements, increase the width of the power traces as much as possible.

2. The orientation of power and ground traces should align with the direction of data flow.

3. A decoupling capacitor of 10~100μF should be placed at the power input of the PCB. A value greater than 100μF is preferable if possible.

2. **Grounding Layout**:

1. Separate the digital ground from the analog ground.

2. The ground traces should be as thick as possible to handle at least three times the maximum current on the PCB, typically 2~3mm in width.

3. In the layout, aim to create a continuous loop for the ground traces to minimize the potential difference across the ground.

3. **Decoupling Capacitor Configuration**:

1. Place a 10~100μF electrolytic capacitor across the power input of the PCB. A value greater than 100μF is ideal if feasible.

2. Use a 0.01~0.1μF ceramic capacitor between Vcc and GND on each integrated circuit. If space is limited, you may use a 1~10μF tantalum capacitor for every 4~10 chips.

3. Components sensitive to noise, such as ROM, RAM, or those with large transient current changes, should also have decoupling capacitors between Vcc and GND.

4. Attach a 0.01μF decoupling capacitor to the “RESET” pin of the microcontroller.

5. Minimize the length of the leads for decoupling capacitors, especially for high-frequency bypass capacitors.

4. **Device Configuration**:

1. The clock input pins of the clock generator, crystal oscillator, and CPU should be positioned as close as possible and separated from low-frequency components.

2. Keep low-current and high-current circuits away from logic circuits as much as possible.

3. Ensure that high-heat generating devices are placed at the top of the PCB within the chassis for better heat dissipation.

5. **Separation of Power Lines, AC Lines, and Signal Lines**:

Power and AC lines should be routed on separate layers or sections of the PCB from the signal traces. If not possible, they should be routed separately from the signal lines.

6. **Additional Layout Principles**:

1. Add a 10kΩ pull-up resistor to the bus to enhance noise immunity.

2. When routing, the address lines should be as short as possible and as direct as possible.

3. Arrange traces on the PCB in a vertical orientation as much as possible to reduce mutual interference.

4. The size of decoupling capacitors is typically calculated as C = 1/F, where F is the data transmission frequency.

5. Unused pins should be connected to Vcc through a 10kΩ pull-up resistor, or tied in parallel with active pins.

6. Heat-producing components (e.g., high-power resistors) should be kept away from temperature-sensitive components like electrolytic capacitors.

7. Full decoding provides better noise immunity than partial decoding.

To mitigate interference from high-power devices affecting the microcontroller’s digital circuits, and vice versa, connect the digital ground and analog ground to a common ground point through a high-frequency choke. A choke consists of a cylindrical ferrite material with several axial holes through which a thick copper wire is threaded and wound around one or two turns. For low-frequency signals, it acts as zero impedance, while for high-frequency signals, it acts as an inductance. (Note that inductors cannot serve as high-frequency chokes due to their high DC resistance.)

When connecting external signal wires, shielded cables are generally used. For high-frequency or digital signals, both ends of the shield should be grounded. For low-frequency analog signals, only one end of the shield should be grounded.

Circuits sensitive to noise and interference, or circuits prone to high-frequency noise, should be shielded with a metal cover. Thin copper provides better shielding against high-frequency noise than ferromagnetic shielding at 500kHz. When securing the shield with screws, be cautious of potential corrosion due to contact between different materials and the resulting voltage difference.

7. **Use of Decoupling Capacitors**


The decoupling capacitor placed between the power supply and ground of an integrated circuit serves two primary functions: it acts as an energy storage capacitor for the integrated circuit, and it also filters out high-frequency noise from the device. In digital circuits, the typical value of a decoupling capacitor is 0.1μF, with a distributed inductance of approximately 5μH. The 0.1μF capacitor, with a distributed inductance of 5μH, has a parallel resonance frequency of around 7MHz. This means it effectively decouples noise below 10MHz but has little impact on noise above 40MHz.

Capacitors with values of 1μF and 10μF have higher parallel resonance frequencies, typically above 20MHz, making them more effective at filtering high-frequency noise.

For every 10 integrated circuits, an additional charge/discharge or energy storage capacitor of about 10μF should be included. It is recommended to avoid using electrolytic capacitors, as they are wound from two layers of film, which at high frequencies behave like inductors. Tantalum or polycarbonate capacitors are a better choice.

The selection of decoupling capacitors is not highly critical. A practical approach is to follow the formula C=1/F, where 0.1μF is used for 10MHz noise and 0.01μF for 100MHz noise.

When soldering decoupling capacitors, keep the leads as short as possible. Long leads can cause the capacitor to self-resonate. For example, a 1000pF ceramic capacitor with a lead length of 6.3mm has a self-resonant frequency of around 35MHz, but with a lead length of 12.6mm, the self-resonant frequency drops to 32MHz.

**Eight Tips for Reducing Noise and Electromagnetic Interference:**

**PCB Anti-Interference Design Principles:**

1. Use series resistors to reduce the edge transition rates in the control circuit.

2. Ensure the potential around the clock signal circuit is as close to ground as possible. Encircle the clock area with ground traces, and keep the clock traces as short as possible.

3. Always ground the positive input of unused operational amplifiers and connect the negative input to the output terminal.

4. Avoid leaving unused gate circuit outputs floating.

5. Use 45° bends for traces instead of 90° bends to reduce external radiation and signal coupling at high frequencies.

6. A clock line running perpendicular to the I/O lines will cause less interference compared to one that runs parallel to them.

7. Keep component leads as short as possible to minimize inductive effects.

8. Avoid routing traces beneath the quartz crystal or components sensitive to noise.

9. Do not create a current loop around sensitive signal circuits or ground planes of low-frequency circuits.

10. When necessary, add ferrite high-frequency chokes to isolate signals, noise, power, and ground.

The PCB manufacturer introduces a distributed capacitance of 2pF to 10pF through its packaging materials. A connector on the circuit board typically has a distributed inductance of 5 to 20μH, and a 24-pin dual-in-line integrated circuit socket adds a distributed inductance ranging from 4μH to 18μH.

This describes the typical circuit distribution found in PCB manufacturing.
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