1. Regarding signal return and cross-segmentation in high-speed PCB boards, we present a simplified scenario here. Ground return, power return, and several cross-segmentation issues are discussed in connection with the following diagram. The layer spacing has been increased for clarity.
IC1 is the signal output terminal, while IC2 acts as the signal input terminal (for the sake of simplicity, we assume that the receiving terminal has a lower connection resistance). The third layer functions as the ground layer, with both IC1 and IC2 being grounded through this layer. The top layer in the upper right corner is the power plane, which connects to the positive pole of the power supply. Capacitors C1 and C2 serve as decoupling capacitors for IC1 and IC2 respectively. The power supply and ground pins shown in the figure represent the power supply and ground for the transmitting and receiving signal terminals.
At low frequencies, when the S1 terminal outputs a high level, the complete current loop is as follows: the power supply connects to the VCC power plane through a wire, then enters IC1 through the orange pathway. From there, it exits through the S1 terminal and reaches IC2 through the R1 terminal along the second layer of wire. It then enters the GND layer and returns to the negative pole of the power supply via the red pathway.
However, at high frequencies, the characteristics of signal distribution on the PCB have a significant impact. The issue of ground return is commonly encountered in high-frequency signals. When there is an increased current in the signal line from S1 to R1, the external magnetic field changes rapidly, inducing a reverse current in nearby conductors. If the ground plane on the third layer is fully connected, there will be a current indicated by a blue dotted line on the ground plane. Similarly, if the TOP layer has a complete power plane, there will also be a current flowing along the blue dotted pathway on the top layer. Consequently, a current loop forms in the signal loop, leading to energy radiation and the ability to couple with external signals. (The skin effect at high frequencies also causes energy to radiate outward, operating on the same principle.)
Since high-frequency signal levels and currents change rapidly but have short periods, the energy required is not substantial. Therefore, the chip is powered by the decoupling capacitor placed close to it. When C1 is sufficiently large and has a fast response (typically using ceramic capacitors with very low ESR values, as their ESR is lower compared to tantalum capacitors), the orange pathway on the top layer and the red pathway on the GND layer can be considered negligible (there is a current related to the power supply of the entire board, but not the current related to the illustrated signal).
1. Therefore, based on the environment depicted in the figure, the current follows this path: from the positive terminal of C1 -> VCC of IC1 -> S1 -> L2 signal line -> R1 -> GND of IC2 -> via hole -> $ of the GND layer Path -> Via -> Capacitor Negative. In this configuration, a vertical equivalent current is evident, inducing a magnetic field within the torus. This setup is susceptible to external interference due to its coupling properties.
2. In the scenario where the signal illustrated is a clock signal, accompanied by a set of 8-bit data lines in parallel, supplied by the same power source within the same chip, the current return path remains consistent. However, if the data lines switch simultaneously in the same direction, it may lead to a significant reverse current induced on the clock line. Improper matching of clock lines can result in detrimental crosstalk, affecting the integrity of the clock signal.
3. The magnitude of this crosstalk is not directly correlated with the level of the interference source but rather with the rate of change of current from the interference source. For a purely resistive load, crosstalk current is proportional to dI/dt=dV /( T10%-90%*R). Here, dI/dt (current rate of change), dV (interference source swing), and R (interference source load) are parameters of the interference source (in the case of a capacitive load, dI/dt is inversely proportional to T10%-90% squared).
4. Notably, low-speed signals may exhibit significant crosstalk, challenging the assumption that lower frequency signals necessarily incur less interference. Therefore, careful consideration of edge cases is imperative.
5. Signals with steep edges contain numerous harmonic components and exhibit considerable amplitude at each frequency multiplication point. Hence, when selecting devices, it’s essential not to blindly opt for chips with fast switching speeds. Such choices may escalate costs and exacerbate crosstalk and electromagnetic compatibility (EMC) issues.
6. Any adjacent power plane or suitable capacitor-equipped plane across the signal can serve as a return path to ground, offering a low reactance pathway. Typically, transceiver chip IO power supplies share common connections and are accompanied by 0.01-0.1uF decoupling capacitors to ground at both ends of the signal, amplifying the return flow effect of the power plane, second only to the ground plane.
7. However, when utilizing alternative power planes for return flow, lacking a low-reactance path to ground at both ends of the signal may necessitate a longer return path. This elongated path, common to adjacent signals, mimics crosstalk effects, impacting signal integrity.
8. To mitigate inevitable cross-power splitting situations, employing high-pass filters like a 10-ohm resistor in series with a 680p capacitor can be effective. These filters provide a high-frequency return path while isolating low-frequency crosstalk between planes. The specific values depend on signal characteristics.
9. In scenarios where other planes are utilized for return, adding small capacitors to ground at both ends of the signal can facilitate a return path, albeit this approach may be challenging due to space constraints around terminals typically occupied by matching resistors and decoupling capacitors on the PCB.
IC1 is the signal output terminal, while IC2 acts as the signal input terminal (for the sake of simplicity, we assume that the receiving terminal has a lower connection resistance). The third layer functions as the ground layer, with both IC1 and IC2 being grounded through this layer. The top layer in the upper right corner is the power plane, which connects to the positive pole of the power supply. Capacitors C1 and C2 serve as decoupling capacitors for IC1 and IC2 respectively. The power supply and ground pins shown in the figure represent the power supply and ground for the transmitting and receiving signal terminals.
At low frequencies, when the S1 terminal outputs a high level, the complete current loop is as follows: the power supply connects to the VCC power plane through a wire, then enters IC1 through the orange pathway. From there, it exits through the S1 terminal and reaches IC2 through the R1 terminal along the second layer of wire. It then enters the GND layer and returns to the negative pole of the power supply via the red pathway.
However, at high frequencies, the characteristics of signal distribution on the PCB have a significant impact. The issue of ground return is commonly encountered in high-frequency signals. When there is an increased current in the signal line from S1 to R1, the external magnetic field changes rapidly, inducing a reverse current in nearby conductors. If the ground plane on the third layer is fully connected, there will be a current indicated by a blue dotted line on the ground plane. Similarly, if the TOP layer has a complete power plane, there will also be a current flowing along the blue dotted pathway on the top layer. Consequently, a current loop forms in the signal loop, leading to energy radiation and the ability to couple with external signals. (The skin effect at high frequencies also causes energy to radiate outward, operating on the same principle.)
Since high-frequency signal levels and currents change rapidly but have short periods, the energy required is not substantial. Therefore, the chip is powered by the decoupling capacitor placed close to it. When C1 is sufficiently large and has a fast response (typically using ceramic capacitors with very low ESR values, as their ESR is lower compared to tantalum capacitors), the orange pathway on the top layer and the red pathway on the GND layer can be considered negligible (there is a current related to the power supply of the entire board, but not the current related to the illustrated signal).
1. Therefore, based on the environment depicted in the figure, the current follows this path: from the positive terminal of C1 -> VCC of IC1 -> S1 -> L2 signal line -> R1 -> GND of IC2 -> via hole -> $ of the GND layer Path -> Via -> Capacitor Negative. In this configuration, a vertical equivalent current is evident, inducing a magnetic field within the torus. This setup is susceptible to external interference due to its coupling properties.
2. In the scenario where the signal illustrated is a clock signal, accompanied by a set of 8-bit data lines in parallel, supplied by the same power source within the same chip, the current return path remains consistent. However, if the data lines switch simultaneously in the same direction, it may lead to a significant reverse current induced on the clock line. Improper matching of clock lines can result in detrimental crosstalk, affecting the integrity of the clock signal.
3. The magnitude of this crosstalk is not directly correlated with the level of the interference source but rather with the rate of change of current from the interference source. For a purely resistive load, crosstalk current is proportional to dI/dt=dV /( T10%-90%*R). Here, dI/dt (current rate of change), dV (interference source swing), and R (interference source load) are parameters of the interference source (in the case of a capacitive load, dI/dt is inversely proportional to T10%-90% squared).
4. Notably, low-speed signals may exhibit significant crosstalk, challenging the assumption that lower frequency signals necessarily incur less interference. Therefore, careful consideration of edge cases is imperative.
5. Signals with steep edges contain numerous harmonic components and exhibit considerable amplitude at each frequency multiplication point. Hence, when selecting devices, it’s essential not to blindly opt for chips with fast switching speeds. Such choices may escalate costs and exacerbate crosstalk and electromagnetic compatibility (EMC) issues.
6. Any adjacent power plane or suitable capacitor-equipped plane across the signal can serve as a return path to ground, offering a low reactance pathway. Typically, transceiver chip IO power supplies share common connections and are accompanied by 0.01-0.1uF decoupling capacitors to ground at both ends of the signal, amplifying the return flow effect of the power plane, second only to the ground plane.
7. However, when utilizing alternative power planes for return flow, lacking a low-reactance path to ground at both ends of the signal may necessitate a longer return path. This elongated path, common to adjacent signals, mimics crosstalk effects, impacting signal integrity.
8. To mitigate inevitable cross-power splitting situations, employing high-pass filters like a 10-ohm resistor in series with a 680p capacitor can be effective. These filters provide a high-frequency return path while isolating low-frequency crosstalk between planes. The specific values depend on signal characteristics.
9. In scenarios where other planes are utilized for return, adding small capacitors to ground at both ends of the signal can facilitate a return path, albeit this approach may be challenging due to space constraints around terminals typically occupied by matching resistors and decoupling capacitors on the PCB.
