Surface Mount (SMT) technology has evolved from pin in line packaging, offering significant advantages in reducing the complexity of PCB design and decreasing its overall size.
In traditional pin insert packaging, a special hole needs to be made in the PCB to accommodate the pin size (FootPrint) of the integrated circuit. This allows the main part of the integrated circuit to be placed on one side of the PCB, while the pins are soldered to the other side to form the circuit connection, consuming space on both sides of the PCB.
For multilayer PCBs, special holes need to be made on each layer, increasing the complexity of the design. In contrast, SMT packaged integrated circuits only require placement and soldering on one side of the PCB, eliminating the need for special holes and reducing the difficulty of PCB design. Additionally, SMT packaging allows for smaller sizes, increasing the density of ICs on the PCB.
There are different types of SMT packaging, including single-ended (pins on one side), dual (pins on both sides), quad (pins on four sides), bottom (pins below), BGA (rectangular pin arrangement), and others based on pin position.
MOSFET Packaging Forms and Technologies for Mainboard
Single-ended (pins on one side): This type of packaging features all pins on one side, usually with a small number of pins. It can be further categorized into thermal enhanced, such as power triodes with three pins in a row and a large heatsink, and COF (Chip on Film), which is directly attached to a flexible circuit board using flip chip technology and then encapsulated with stop coating. COF is thin and light, making it widely used in LCDs to meet the demand for increased resolution.
The downside is that film is very expensive, as is the mounter.
Dual (pins on both sides), as shown in Figure 3. This packaging type features all pins on both sides, with a moderate pin count. It encompasses various packaging types such as SOT (Smalloutline Transistor), SOP (Small Outline Package), SOJ (Small 0outline Package J-bent lea (1), SS() P (Shrink Small 0outline Package), HSOP (Heat sink Small Outline Package), and others.
The SOT series mainly includes SOT-23, SOT-223, SOT-25, SOT-26, SOT323, SOT-89, etc. As electronic products continue to shrink in size, the semiconductor devices used inside must also become smaller. Smaller semiconductor devices enable electronic products to be smaller, lighter, more portable, and contain more functions in the same size. The value of semiconductor devices is best reflected in the space occupied by PCB and the total package height. Optimizing these parameters allows for a more compact design on a smaller PCB. SOT packaging greatly reduces both the height and footprint of the PCB. For example, SOT883 is widely used in small daily consumer appliances such as mobile phones, cameras, and MP3 players.
Small size patch package (SOP: Small 0utline Package). Royal Philips of the Netherlands developed the small SMD package SOP in the 1970s, which later led to the development of SOJ (J-pin small footprint package), TSOP (thin small footprint package), VSOP (very small footprint package), SS() P (reduced footprint SOP), TSSOP (thin reduced footprint SOP), SOT (small footprint transistor), and SOIC (small footprint integrated circuit), among others. The typical lead spacing of SOP is 1.27 mm, and the pin count is within dozens.
TSOP (Thin Small Outline Package) is a type that appeared in the 1980s. The biggest difference between TSOP and SOP is its 1 mm thickness, which is 1/3 of that of SOJ. Due to its thin and small package, it is suitable for high-frequency use, with strong operability and high reliability. Most SDRAM memory chips adopt this packaging method. The TSOP memory package is rectangular, with I/O pins around the package chip. In the TSOP packaging mode, memory components are soldered on the PCB through chip pins, with a small contact area between the solder joint and the PCB, making it relatively difficult for the chip to transfer heat to the PCB design. Additionally, when the memory of TSOP package exceeds 150MHz, there will be significant signal interference and electromagnetic interference.
Small Outline J-Led Package (SOJ) features pins led out from both sides of the package body in a J shape downward and directly pasted on the surface of the printed circuit board. They are mainly used in memory LSI circuits such as DRAM and SRAM, with a center distance of 1.27 mm and a lead count of 20-40.
In traditional pin insert packaging, a special hole needs to be made in the PCB to accommodate the pin size (FootPrint) of the integrated circuit. This allows the main part of the integrated circuit to be placed on one side of the PCB, while the pins are soldered to the other side to form the circuit connection, consuming space on both sides of the PCB.
For multilayer PCBs, special holes need to be made on each layer, increasing the complexity of the design. In contrast, SMT packaged integrated circuits only require placement and soldering on one side of the PCB, eliminating the need for special holes and reducing the difficulty of PCB design. Additionally, SMT packaging allows for smaller sizes, increasing the density of ICs on the PCB.
There are different types of SMT packaging, including single-ended (pins on one side), dual (pins on both sides), quad (pins on four sides), bottom (pins below), BGA (rectangular pin arrangement), and others based on pin position.
MOSFET Packaging Forms and Technologies for Mainboard
Single-ended (pins on one side): This type of packaging features all pins on one side, usually with a small number of pins. It can be further categorized into thermal enhanced, such as power triodes with three pins in a row and a large heatsink, and COF (Chip on Film), which is directly attached to a flexible circuit board using flip chip technology and then encapsulated with stop coating. COF is thin and light, making it widely used in LCDs to meet the demand for increased resolution.
The downside is that film is very expensive, as is the mounter.
Dual (pins on both sides), as shown in Figure 3. This packaging type features all pins on both sides, with a moderate pin count. It encompasses various packaging types such as SOT (Smalloutline Transistor), SOP (Small Outline Package), SOJ (Small 0outline Package J-bent lea (1), SS() P (Shrink Small 0outline Package), HSOP (Heat sink Small Outline Package), and others.
The SOT series mainly includes SOT-23, SOT-223, SOT-25, SOT-26, SOT323, SOT-89, etc. As electronic products continue to shrink in size, the semiconductor devices used inside must also become smaller. Smaller semiconductor devices enable electronic products to be smaller, lighter, more portable, and contain more functions in the same size. The value of semiconductor devices is best reflected in the space occupied by PCB and the total package height. Optimizing these parameters allows for a more compact design on a smaller PCB. SOT packaging greatly reduces both the height and footprint of the PCB. For example, SOT883 is widely used in small daily consumer appliances such as mobile phones, cameras, and MP3 players.
Small size patch package (SOP: Small 0utline Package). Royal Philips of the Netherlands developed the small SMD package SOP in the 1970s, which later led to the development of SOJ (J-pin small footprint package), TSOP (thin small footprint package), VSOP (very small footprint package), SS() P (reduced footprint SOP), TSSOP (thin reduced footprint SOP), SOT (small footprint transistor), and SOIC (small footprint integrated circuit), among others. The typical lead spacing of SOP is 1.27 mm, and the pin count is within dozens.
TSOP (Thin Small Outline Package) is a type that appeared in the 1980s. The biggest difference between TSOP and SOP is its 1 mm thickness, which is 1/3 of that of SOJ. Due to its thin and small package, it is suitable for high-frequency use, with strong operability and high reliability. Most SDRAM memory chips adopt this packaging method. The TSOP memory package is rectangular, with I/O pins around the package chip. In the TSOP packaging mode, memory components are soldered on the PCB through chip pins, with a small contact area between the solder joint and the PCB, making it relatively difficult for the chip to transfer heat to the PCB design. Additionally, when the memory of TSOP package exceeds 150MHz, there will be significant signal interference and electromagnetic interference.
Small Outline J-Led Package (SOJ) features pins led out from both sides of the package body in a J shape downward and directly pasted on the surface of the printed circuit board. They are mainly used in memory LSI circuits such as DRAM and SRAM, with a center distance of 1.27 mm and a lead count of 20-40.
