There are many ways to solve EMI problems. Modern EMI suppression methods include: using EMI suppression coatings, selecting appropriate EMI suppression parts, and EMI simulation design. Starting from the most basic PCB layout, this article discusses the role and design techniques of PCB layered stacking in controlling EMI radiation.
Power bus
Properly placing capacitors of appropriate capacity near the power supply pins of the IC can make the IC output voltage respond faster. However, this only partially addresses the issue. Due to the limited frequency response of capacitors, they fail to provide the harmonic power necessary for clean IC output across the full frequency band. Additionally, transient voltages on the power bus generate voltage drops across decoupling path inductances, which are primary sources of common-mode EMI interference. How do we address these challenges?
For ICs on our circuit board, the power layer surrounding the IC acts like a high-frequency capacitor, capturing energy leaked by discrete capacitors to provide clean high-frequency output. Moreover, a low-inductance power layer minimizes transient signals, thereby reducing common-mode EMI. Ensuring the connection between the power layer and IC power pin is as short as possible is crucial, given the increasingly rapid rise times of digital signals. Ideally, direct connection to the IC power pin pad is optimal, a topic we’ll delve into separately. To effectively manage common-mode EMI, the power plane must facilitate decoupling and maintain low inductance. This necessitates a well-designed pair of power planes. One might inquire, what constitutes ‘well-designed’? The answer hinges on power plane layering, inter-layer materials, and operational frequency (related to IC rise times).
Generally, the spacing of the power layer is 6 mils, and the interlayer material is FR4. The equivalent capacitance of the power layer per square inch is approximately 75 pF. Clearly, smaller layer spacings yield greater capacitance. While devices with rise times of 100 to 300 ps are uncommon, they are becoming more prevalent due to current IC development speeds. For circuits with these rise times, a 3 mil layer spacing is no longer suitable for most applications. At that point, layering technologies with sub-1 mil spacing and dielectric materials of higher permittivity must be employed. Ceramics and ceramic plastics can now fulfill the design requirements of circuits with 100 to 300 ps rise times. Although new materials and methods may emerge, today’s typical circuits with rise times of 1 to 3 ns usually suffice with 3 to 6 mil layer spacing and FR4 dielectrics. These configurations effectively manage high-end harmonics and minimize transient signals, thereby significantly reducing common mode EMI. This article’s PCB layer stacking examples will assume layer spacings of 3 to 6 mils.
From a signal trace perspective, an effective layering strategy involves consolidating all signal traces onto one or a few layers adjacent to power or ground layers. For power distribution, an optimal layering strategy requires placing the power layer adjacent to the ground layer with minimal spacing—a practice referred to as “layering.”
What PCB stacking strategy effectively shields and suppresses EMI? The following stacking schemes assume that power supply currents flow through a single layer, while single or multiple voltages are distributed across different parts of the same layer. Multiple power layer cases will be discussed later.
4-layer board
Several issues may arise with traditional 4-layer board designs. Despite having signal layers on the outer layers and power/ground layers on the inner layers, the distance between power and ground layers remains excessive at 62 mils thick.
To meet cost requirements initially, consider two alternative designs for traditional 4-layer boards. These solutions can enhance EMI suppression performance but are only suitable for low-component-density applications with ample area around components for required power copper layers. The preferred solution involves all outer PCB layers serving as ground layers, with the middle two layers dedicated to signals and power. Routing power supply on the signal layer with wide lines reduces power supply current path impedance and ensures low impedance for signal microstrip paths. This represents the optimal 4-layer PCB structure for EMI control. In the second scheme, outer layers serve as power and ground, with the middle two layers as signal layers. Though an improvement over traditional 4-layer boards, this scheme suffers from interlayer impedance issues similar to traditional designs. Careful placement of traces beneath power and ground copper islands is essential for impedance control, along with maximizing interconnection of copper islands to ensure DC and low-frequency connectivity.
6-layer board
For higher component density than a 4-layer board, a 6-layer board is preferable. However, some stacking schemes in 6-layer board designs may inadequately shield electromagnetic fields and have minimal impact on transient signal reduction in power bus.
10-layer board
Due to thin insulation layers between multilayer boards, impedance among the 10 or 12 layers is very low. Achieving excellent signal integrity is feasible provided proper layering and stacking. Manufacturing 12-layer boards at 62 mil thickness is challenging, with few manufacturers capable of processing such boards.
In the absence of closely located via holes, increased inductance and reduced capacitance are inevitable, leading to heightened EMI. When signal lines must traverse PCB wiring layers via vias, ground vias should be positioned near vias to facilitate smooth signal return to appropriate grounding layers. Signal loops on layers 4 and 7, for instance, return via power or ground layers (layers 5 or 6) where capacitive coupling between power and ground layers is optimal, enabling efficient signal transmission.
Power bus
Properly placing capacitors of appropriate capacity near the power supply pins of the IC can make the IC output voltage respond faster. However, this only partially addresses the issue. Due to the limited frequency response of capacitors, they fail to provide the harmonic power necessary for clean IC output across the full frequency band. Additionally, transient voltages on the power bus generate voltage drops across decoupling path inductances, which are primary sources of common-mode EMI interference. How do we address these challenges?
For ICs on our circuit board, the power layer surrounding the IC acts like a high-frequency capacitor, capturing energy leaked by discrete capacitors to provide clean high-frequency output. Moreover, a low-inductance power layer minimizes transient signals, thereby reducing common-mode EMI. Ensuring the connection between the power layer and IC power pin is as short as possible is crucial, given the increasingly rapid rise times of digital signals. Ideally, direct connection to the IC power pin pad is optimal, a topic we’ll delve into separately. To effectively manage common-mode EMI, the power plane must facilitate decoupling and maintain low inductance. This necessitates a well-designed pair of power planes. One might inquire, what constitutes ‘well-designed’? The answer hinges on power plane layering, inter-layer materials, and operational frequency (related to IC rise times).
Generally, the spacing of the power layer is 6 mils, and the interlayer material is FR4. The equivalent capacitance of the power layer per square inch is approximately 75 pF. Clearly, smaller layer spacings yield greater capacitance. While devices with rise times of 100 to 300 ps are uncommon, they are becoming more prevalent due to current IC development speeds. For circuits with these rise times, a 3 mil layer spacing is no longer suitable for most applications. At that point, layering technologies with sub-1 mil spacing and dielectric materials of higher permittivity must be employed. Ceramics and ceramic plastics can now fulfill the design requirements of circuits with 100 to 300 ps rise times. Although new materials and methods may emerge, today’s typical circuits with rise times of 1 to 3 ns usually suffice with 3 to 6 mil layer spacing and FR4 dielectrics. These configurations effectively manage high-end harmonics and minimize transient signals, thereby significantly reducing common mode EMI. This article’s PCB layer stacking examples will assume layer spacings of 3 to 6 mils.
From a signal trace perspective, an effective layering strategy involves consolidating all signal traces onto one or a few layers adjacent to power or ground layers. For power distribution, an optimal layering strategy requires placing the power layer adjacent to the ground layer with minimal spacing—a practice referred to as “layering.”
What PCB stacking strategy effectively shields and suppresses EMI? The following stacking schemes assume that power supply currents flow through a single layer, while single or multiple voltages are distributed across different parts of the same layer. Multiple power layer cases will be discussed later.
4-layer board
Several issues may arise with traditional 4-layer board designs. Despite having signal layers on the outer layers and power/ground layers on the inner layers, the distance between power and ground layers remains excessive at 62 mils thick.
To meet cost requirements initially, consider two alternative designs for traditional 4-layer boards. These solutions can enhance EMI suppression performance but are only suitable for low-component-density applications with ample area around components for required power copper layers. The preferred solution involves all outer PCB layers serving as ground layers, with the middle two layers dedicated to signals and power. Routing power supply on the signal layer with wide lines reduces power supply current path impedance and ensures low impedance for signal microstrip paths. This represents the optimal 4-layer PCB structure for EMI control. In the second scheme, outer layers serve as power and ground, with the middle two layers as signal layers. Though an improvement over traditional 4-layer boards, this scheme suffers from interlayer impedance issues similar to traditional designs. Careful placement of traces beneath power and ground copper islands is essential for impedance control, along with maximizing interconnection of copper islands to ensure DC and low-frequency connectivity.
6-layer board
For higher component density than a 4-layer board, a 6-layer board is preferable. However, some stacking schemes in 6-layer board designs may inadequately shield electromagnetic fields and have minimal impact on transient signal reduction in power bus.
10-layer board
Due to thin insulation layers between multilayer boards, impedance among the 10 or 12 layers is very low. Achieving excellent signal integrity is feasible provided proper layering and stacking. Manufacturing 12-layer boards at 62 mil thickness is challenging, with few manufacturers capable of processing such boards.
In the absence of closely located via holes, increased inductance and reduced capacitance are inevitable, leading to heightened EMI. When signal lines must traverse PCB wiring layers via vias, ground vias should be positioned near vias to facilitate smooth signal return to appropriate grounding layers. Signal loops on layers 4 and 7, for instance, return via power or ground layers (layers 5 or 6) where capacitive coupling between power and ground layers is optimal, enabling efficient signal transmission.
