It is important to note that these extracted values are a fundamental component of the IBIS model.
**Signal Integrity Issues**
When observing digital signals at both ends of a transmission line, designers may be surprised by the results when the signal reaches the PCB trace. Over relatively long distances, the electrical signal behaves more like a traveling wave than an instantaneous voltage change. A good analogy for simulating wave behavior on a circuit board is CHICHENGPO (waves in a pool). When two water bodies with the same volume meet, they pass through each other smoothly due to matching “impedance.” However, when there is a noticeable difference in the impedance of the dividing wall, waves are reflected in the opposite direction. Similarly, an electrical signal injected into a PCB trace experiences this phenomenon when there is an impedance mismatch.
Figure 1 illustrates a PCB setup with mismatched end impedance. In this example, a microcontroller (TI MSP430™) sends a clock signal to the TI ADS8326 ADC, which, in turn, sends conversion data back to the MSP430. Figure 2 demonstrates the reflections caused by these impedance mismatches. These reflections can lead to significant signal integrity issues along the transmission line traces.
1. Allowing PCB trace resistance matching at one or both ends can significantly reduce signal reflections.
2. To address system resistance and impedance matching issues, designers need to understand the impedance characteristics of integrated circuits (ICs) as well as the impedance of PCB traces that act as transmission lines.
3. Once these characteristics are understood, designers can model each connection unit as a distributed transmission line. Transmission lines provide a variety of circuit functions, ranging from single-ended and differential terminal equipment to open-drain output devices. This article primarily focuses on single-ended transmission lines, where the driver employs a push-pull output design.
4. Additionally, the following IC pin specifications are required:
– Transmitter output resistance ( Z_T ) (Ω)
– Transmitter rise time ( t_{Rise} ) and fall time ( t_{Fall} ) (seconds)
– Receiver input resistance ( Z_R ) (Ω)
– Receiver pin capacitance ( C_{R_Pin} ) (F)
These specifications are typically not included in the IC manufacturer’s datasheet.
5. As will be discussed, all of these values can be derived from the IC’s IBIS model during PCB design, enabling the simulation of the PCB transmission path.
6. The following parameters are used to define transmission lines:
– Characteristic impedance ( Z_0 ) (Ω)
– Propagation delay ( D ) (ps/inch)
– Track propagation delay ( t_D ) (ps)
– Track length ( text{LENGTH} ) (inches)
Depending on the specific PCB design, this list may include additional variables. For example, the PCB design could incorporate a backplane with multiple transmission/reception points.
7. The transmission line routing depends on the specific PCB design. Generally, the characteristic impedance ( Z_0 ) for an FR-4 board ranges from 50 to 75 ohms, and the propagation delay ( D ) ranges from 140 to 180 ps/inch. The actual values for ( Z_0 ) and ( D ) are influenced by the material properties and physical dimensions of the transmission line.
8. The line propagation delay for a specific circuit board can be calculated as follows:
[
t_D = D times text{LENGTH}
]
For an FR-4 board, the reasonable propagation delay of a linear trace (as shown in Figure 4) is 178 ps/inch, with a characteristic impedance of 50 ohms.
9. By measuring the inductance and capacitance of the trace and inserting these values into the appropriate formula, we can validate this result on the circuit board. The parameters involved are: ( C_{TR} ), the trace capacitance in farads per inch, and ( L_{TR} ), the trace inductance in nanohenries per inch. The dielectric constant of air is denoted as ( epsilon_r ), and ( epsilon_R ) represents the material’s dielectric constant.
10. For instance, if a microwave transmission line on the PCB has a capacitance of 2.6 pF/inch and an inductance of 6.4 nH/inch, the propagation delay is 129 ps/inch and the characteristic impedance ( Z_0 ) is 49.4 Ω.
11. **Comparison of Aggregate Circuits and Distributed Circuits:** Once the transmission line has been defined, the next step is to determine whether the circuit layout represents an aggregated or distributed system. Typically, aggregated systems are small in size, while distributed circuits occupy more board space. A small circuit has an effective length (LENGTH), and its signal is smaller than the fastest electrical characteristic.
12. To qualify as an aggregated system, the circuit on the PCB must meet the following requirements:
– ( t_{Rise} ), the rise time in seconds.
13. After the aggregated circuit is implemented on the PCB, termination strategy becomes less of a concern. Essentially, we assume that the drive signal sent to the transmission line reaches the receiver instantaneously.
14. The data structure of the IBIS model is based on the power supply voltage range of the IC. The IBIS model includes three, six, or nine corner data points. These corners are determined by the silicon process, power supply voltage, and junction temperature. The specific process/voltage/temperature (PVT) SPICE model is essential for creating an accurate IBIS model. Variations in ratings, silicon processes, and other factors lead to different model strengths and weaknesses. The designer sets the voltage according to the component’s power requirements, varying between the rated, minimum, and maximum values.
15. Lastly, based on the component’s rated temperature range, power consumption, and junction-to-ambient thermal resistance ( theta_{JA} ), the temperature setting for the silicon junction is determined. Table 1 presents examples of the three PVT variables and their relation to TI’s 24-bit biopotential measurement ADC ADS129x series CMOS process. These variables are used to perform six SPICE simulations. The first and fourth simulations use the rated process model, rated voltage, and junction temperature at room temperature. The second and fifth simulations apply a weak process model with low voltage and high junction temperature, while the third and sixth use a strong process model with high voltage and low junction temperature.
16. The relationship between the PVT values maps the optimal corner for the CMOS process.
17. **Finding and/or Calculating Transmitter Specifications:** The specified transmitter parameters for signal integrity evaluation include output impedance ( Z_T ) and rise time ( t_{Rise} ) and ( t_{Fall} ). Figure 5 shows the TI ADS1296 package (ads129x.ibs), which lists the self-IBIS model files. The impedance used for generating the signal is specified under the [Pin] keyword, which also appears in the buffer model (not shown).
18. The rise time is located in the transient section of the IBIS model data list.
19. **Input and Output Pin Impedance:** The impedance of any signal pin is a combination of the model impedance, package inductance, and capacitance. In Figure 5, the keywords “[Component]”, “[Manufacturer]”, and “[Package]” describe the specific package type, such as a 64-pin PBGA (ZXG). The inductance and capacitance for a specific pin are listed under the “[Pin]” keyword. For example, at pin 5E, you can find the GPIO4 signal, along with the values for ( L_{pin} ) and ( C_{pin} ).
20. The ( L_{pin} ) (pin inductance) and ( C_{pin} ) (pin capacitance) values for the signal and package are 1.4891 nH and 0.28001 pF, respectively. The second important capacitance value is the silicon capacitance, ( C_{comp} ), which can be found under the “[Model]” keyword in the DIO_33 list of the ads129x.ibs file (see Figure 6). ( C_{comp} ) represents the capacitance of the DIO buffer, with a power supply voltage of 3.3V. The “|” symbol indicates a comment; thus, the effective ( C_{comp} ) value in this list is 3.0727220e-12 F (typical), 2.3187130e-12 F (minimum), and 3.8529520e-12 F (maximum), which PCB designers can select from.
21. **Using IBIS for Transmission Line Design:** This article starts with a PCB design featuring mismatched end impedances. The PCB manufacturer, using the IBIS model, identifies key components of the transmission issue. There should be a solution to address this problem.
22. **Termination Strategy and Waveform Correction:** To design a PCB transmission line, the first step is to gather information from the PCB product manual. The next step is to examine the IBIS model for parameters that are not included in the specification, such as input/output impedance, rise time, and input/output capacitance. When entering the hardware phase, the IBIS model should be used to identify key product specifications and simulate the final design.
