With the continuous development of display technology, true-color LCD displays are gradually becoming essential in PCB embedded display systems due to their advantages of high resolution, high contrast, and clarity. Currently, there are primarily two approaches to implementing LCD controllers on PCB embedded platforms: ARM-based embedded LCD controllers and standalone control devices. However, both methods have their drawbacks. Using embedded controllers can burden the PCB processor and constrain the display frame rate. External PCB control devices, on the other hand, are expensive and often specialized, making them less adaptable to various types of LCD screens.
Based on this problem, a design scheme for an LCD controller based on ARM and FPGA is proposed. This scheme aims to enhance video memory writing rates and relieve processor burden by utilizing the Framebuffer device under the LINUX OS. Additionally, FPGA is employed to implement the LCD controller, offering advantages such as a short development cycle, low power consumption, and flexible portability across various small and medium-sized LCD screens.
The system comprises a microcontroller, FPGA (LCD controller), storage unit, and peripheral interface, as illustrated in Figure 1.
The operational flow of the system is as follows: under timing control signals generated by the FPGA’s internal timing circuitry, the LCD controller retrieves display data from the microcontroller via the Framebuffer interface, storing it in the display buffer SRAM. Concurrently, the LCD display accesses display data from the SRAM, directly presenting real-time data through a data format conversion circuit.
The LCD controller, implemented on an FPGA (Altera’s Cvclone series EPlC6Q240), leverages high-speed data transmission I/O interfaces to achieve rapid display memory access, thereby significantly boosting LCD frame rates. Additionally, FPGA serves as a programmable logic device capable of executing complex logic operations and providing intricate control timing. The LCD display used is the LQ035Q3DG01 TFT-LCD with a resolution of 320×240 pixels, transmitting image signals in RGB format.
To ensure efficient performance, the system’s display cache utilizes a 512 KB IS61LV51216AL SRAM module with approximately 10 ns read and write speeds. Given that a frame size is 125 KB (320x240x2/1024), FPGA’s read and write speeds to the display memory meet the system’s requirements at approximately 200 ns.
The main control unit, powered by ATMEL’s AT91RM9200 (9200), operates as the system’s MCU. Based on the ARM920T core running at 180 MHz, it achieves performance levels up to 200 MI/s. The system operates on the open-source LINUX OS, enabling the MCU to handle tasks such as data collection, processing, and external communications. To alleviate processor load and enhance LCD real-time performance, an application method based on the Framebuffer interface under LINUX OS is proposed, optimizing data read rates from the display memory.
The software architecture of the system is divided into two primary components: FPGA-based LCD controller design and Framebuffer driver design under LINUX OS. The LCD controller module includes functionalities such as cache read/write, MCU interface, and LCD timing control.
Regarding TFT-LCD display principles, essential control signals include the pixel clock signal, line/field synchronization signal, and enable signal. With a screen resolution of 320×240 pixels, the refresh rate is set to 60 Hz, resulting in a 60 Hz field synchronization signal (VSYNC). The line synchronization signal (HSYNC) operates at 15 kHz, derived from the VSYNC period of 1/(60×240) s. Similarly, the pixel clock signal (CK) is 5 MHz.
The FPGA utilizes an internal phase-locked loop IP module (PLL) to divide the 50 MHz FPGA clock (F_CLK) by 10, generating the 5 MHz pixel clock signal (CK). The timing control module, designed using Verilog hardware description language and utilizing state machine methodology, produces PCB control signals (VSYNC, HSYNC, ENAB) meeting LCD timing requirements. Verification of timing compliance is conducted using the Quatus II simulation environment.
Regarding PCB data transmission between the LCD controller and microcontroller, data is synchronized under ARM clock control, while the LCD screen accesses SRAM data under the pixel clock signal (CK) control. To manage data transmission between different clock domains, the solution employs an FPGA-designed asynchronous FIFO.
Based on this problem, a design scheme for an LCD controller based on ARM and FPGA is proposed. This scheme aims to enhance video memory writing rates and relieve processor burden by utilizing the Framebuffer device under the LINUX OS. Additionally, FPGA is employed to implement the LCD controller, offering advantages such as a short development cycle, low power consumption, and flexible portability across various small and medium-sized LCD screens.
The system comprises a microcontroller, FPGA (LCD controller), storage unit, and peripheral interface, as illustrated in Figure 1.
The operational flow of the system is as follows: under timing control signals generated by the FPGA’s internal timing circuitry, the LCD controller retrieves display data from the microcontroller via the Framebuffer interface, storing it in the display buffer SRAM. Concurrently, the LCD display accesses display data from the SRAM, directly presenting real-time data through a data format conversion circuit.
The LCD controller, implemented on an FPGA (Altera’s Cvclone series EPlC6Q240), leverages high-speed data transmission I/O interfaces to achieve rapid display memory access, thereby significantly boosting LCD frame rates. Additionally, FPGA serves as a programmable logic device capable of executing complex logic operations and providing intricate control timing. The LCD display used is the LQ035Q3DG01 TFT-LCD with a resolution of 320×240 pixels, transmitting image signals in RGB format.
To ensure efficient performance, the system’s display cache utilizes a 512 KB IS61LV51216AL SRAM module with approximately 10 ns read and write speeds. Given that a frame size is 125 KB (320x240x2/1024), FPGA’s read and write speeds to the display memory meet the system’s requirements at approximately 200 ns.
The main control unit, powered by ATMEL’s AT91RM9200 (9200), operates as the system’s MCU. Based on the ARM920T core running at 180 MHz, it achieves performance levels up to 200 MI/s. The system operates on the open-source LINUX OS, enabling the MCU to handle tasks such as data collection, processing, and external communications. To alleviate processor load and enhance LCD real-time performance, an application method based on the Framebuffer interface under LINUX OS is proposed, optimizing data read rates from the display memory.
The software architecture of the system is divided into two primary components: FPGA-based LCD controller design and Framebuffer driver design under LINUX OS. The LCD controller module includes functionalities such as cache read/write, MCU interface, and LCD timing control.
Regarding TFT-LCD display principles, essential control signals include the pixel clock signal, line/field synchronization signal, and enable signal. With a screen resolution of 320×240 pixels, the refresh rate is set to 60 Hz, resulting in a 60 Hz field synchronization signal (VSYNC). The line synchronization signal (HSYNC) operates at 15 kHz, derived from the VSYNC period of 1/(60×240) s. Similarly, the pixel clock signal (CK) is 5 MHz.
The FPGA utilizes an internal phase-locked loop IP module (PLL) to divide the 50 MHz FPGA clock (F_CLK) by 10, generating the 5 MHz pixel clock signal (CK). The timing control module, designed using Verilog hardware description language and utilizing state machine methodology, produces PCB control signals (VSYNC, HSYNC, ENAB) meeting LCD timing requirements. Verification of timing compliance is conducted using the Quatus II simulation environment.
Regarding PCB data transmission between the LCD controller and microcontroller, data is synchronized under ARM clock control, while the LCD screen accesses SRAM data under the pixel clock signal (CK) control. To manage data transmission between different clock domains, the solution employs an FPGA-designed asynchronous FIFO.
