A little confusion for some on why there is a difference between a real ‘Power Plane’ assigned to a net, whether split or not, VERSUS a ‘Polygon Fill’ of a net.
Now, let it be understood that some of the latest cad software out there may offer the ability in the polygon fill to erase out the pad around the drill hole around the unconnected filled region, but, it wasn’t happening in Dave example video.  For those who know the inside-out of Kicad who may have a way to do this erasure to gain maximum copper fill around unused pads, please add to this thread, however, my numerous versions of Protel versions cannot perform this feat in any automatic means when using a polygon-fill.

Taking a look at this screenshot, we can see a polygon fill, where traces won fit between pads.

Now look at this power plane.  NOTE this is a negative image, so, the black is copper and green is void, no copper.
You can see that the copper between unwired pads is double to 0.8mm space, but, why?

For the answer, take a look at this screenshot to reveal the reason.  Again, it’s a negative image, so, the black is copper and green is void, no copper.
The spacing is still 0.45mm, but, there are NO PADS on a power plane, just the drill holes, and either copper flows over the hole, or it doesn’t.

Note that the orange is the drill hole size.  On the upper images, white is the drill hole size and grey is the PAD copper around the drill hole.
(Please excuse a minor mistake in the GND connection on the power plane, the green relief voids should have been set further away from the drill hole plus a little thinner.)
Polygon fills may be OK for general large circuits, but, when doing RF and you want maximum unbroken GND plane, or, BGA FPGA with vias so close to one another, the true power planes become necessary for generating unbroken GND&VCC fill around all those compact close together vias which would at many times get broken and chewed up with a polygon-fill like my first example image.