VXSDR-20 is a high-performance microwave software-defined radio (SDR) that operates across a frequency range of 5 to 20 GHz, with a sampling rate of 160 million samples per second. It offers features comparable to other advanced SDRs, including 10-gigabit Ethernet connectivity, support for C and C++ programming, and ongoing integration with Python and GnuRadio. It also allows synchronization across multiple radios, among other capabilities.
Porting applications to this platform is straightforward, and both the software and firmware are open-source. The modular design supports various configurations, including multiple channels, extended or reduced frequency ranges, and adjustable sample rates. Simultaneous full-rate transmit and receive via 10 Gb Ethernet is supported by default, and the system accepts 10 MHz and 1 PPS frequency and time references for synchronization.
Software-defined radios are widely used by experimenters, scientists, and engineers for communication, sensing, navigation, and various other applications. However, commercially available SDRs typically operate below 6 GHz. To meet the needs of a broader frequency range, the creators of the VXSDR-20 developed this system to operate across the 5-20 GHz spectrum, enabling similar functionality at higher frequencies.
The VXSDR-20 is designed to function like any other high-end SDR, but with extended frequency coverage. It is ideal for laboratory research in communication systems and sensing applications, capable of both transmission and reception. The user-friendly host API is designed to ensure that porting from the widely adopted Ettus UHD API is seamless.
Features & Specifications
Analog RF and IF
- 5.0 – 20.0 GHz transmit and receive (usable up to 22 GHz)
- 5 – 9 dB receive noise figure
- 10 – 15 dBm output power
- Low-IF design (160 MHz IF)
- TX output and TX/RX input/output (field-replaceable SMA connectors)
Digital
- 14-bit, 160 MSPS A/D converter for reception
- 16-bit, 160 MSPS D/A converter for transmission
- JESD204B interfaces for data transfer
- Intel Cyclone 10 FPGA (85k – 220k logic elements)
Control and Data Transfer
- 10 gigabit Ethernet interface (SFP+)
- Simultaneous full-rate transmit and receive capabilities
- PPS and 10 MHz inputs for synchronization
Software
- Developed in C++ using boost::asio and boost::lockfree::spsc_queue (for data handling)
- API design similar to UHD, making it easy to integrate with existing code
- Currently supports Linux; Windows and Mac support are under development
- Python bindings are planned for future releases
- GPL v3 licensing planned with code available on GitHub
Power
- 12 V DC power input
- 22 W active power consumption, 16 W idle
Physical Dimensions
- 9.4 inches (23.9 cm) long (including connectors)
- 4.1 inches (10.5 cm) wide
- 1.0 inch (2.4 cm) high
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