1. Define the wiring area to be within 1mm from the edge of the PCB and within 1mm around the mounting hole, where routing is prohibited.
2. The width of power traces should be as large as possible, and no less than 18mil; signal traces should not be narrower than 12mil; CPU input and output traces should be at least 10mil (or 8mil); trace spacing must not be smaller than 10mil.
3. The minimum via size should be 30mil.
4. Ensure that power and ground traces are as radial as possible, and avoid forming any loops with the signal traces.
5. Grounding guidelines:
The minimum loop area rule stipulates that the area enclosed by the signal trace and its return path should be kept as small as possible. A smaller loop area reduces external radiation and minimizes susceptibility to external interference. An example is shown in the figure below:
6. **Crosstalk Control**
Crosstalk refers to the interference between different networks on the PCB, primarily caused by long parallel traces. This interference is due to the distributed capacitance and inductance between the parallel traces. To mitigate crosstalk, the following measures can be implemented:
– Increase the spacing between parallel traces, adhering to the 3W rule.
– Insert a grounded trace between parallel traces.
– Reduce the distance between the signal traces and the ground plane.
7. **Routing Direction Control Rules**
The routing directions of adjacent layers should be orthogonal. Avoid routing different signal lines in the same direction on adjacent layers to minimize inter-layer crosstalk. If this is not possible due to board constraints, especially for high-speed signals, consider using a ground plane to isolate each signal layer, with ground traces separating each signal line. Input and output traces on the PCB should be routed to avoid parallelism, which could lead to feedback. Ideally, a ground trace should be placed between these signals.
8. **Open-Loop Inspection Rules**
It is generally not allowed to leave a trace floating at one end. This is to prevent the “antenna effect” and reduce unwanted electromagnetic radiation and reception, which could result in unpredictable behavior.
9. **Impedance Matching Inspection Rules**
The trace width for a given signal network should remain consistent. Variations in trace width can cause uneven characteristic impedance, leading to signal reflections at high transmission speeds. This situation should be avoided wherever possible. In cases such as connector lead traces or BGA package leads where width changes may be unavoidable, minimize the length of the section with inconsistent impedance.
10. **Closed-Loop Routing Inspection Rules**
Avoid creating signal loops between different layers. Such issues are common in multi-layer PCB designs, and loops can cause radiation interference.
11. **Branch Length Control Rules**
Control the length of trace branches to minimize signal delay. A general guideline is that the delay should be approximately T_delay = Trise/20.
12. **Resonance Control Rules**
This rule applies mainly to high-frequency signal design. The length of a trace should not be an integer multiple of the signal’s wavelength, to avoid resonance effects.
13. **Trace Length Control Rules**
This refers to the “short-line rule.” In PCB design, trace lengths should be kept as short as possible to minimize interference from excessively long traces. This is particularly important for critical signal lines, such as clock traces. These should be placed as far from other components as possible. When driving multiple devices, network topology should be determined based on the specific application requirements.
2. The width of power traces should be as large as possible, and no less than 18mil; signal traces should not be narrower than 12mil; CPU input and output traces should be at least 10mil (or 8mil); trace spacing must not be smaller than 10mil.
3. The minimum via size should be 30mil.
4. Ensure that power and ground traces are as radial as possible, and avoid forming any loops with the signal traces.
5. Grounding guidelines:
The minimum loop area rule stipulates that the area enclosed by the signal trace and its return path should be kept as small as possible. A smaller loop area reduces external radiation and minimizes susceptibility to external interference. An example is shown in the figure below:
6. **Crosstalk Control**
Crosstalk refers to the interference between different networks on the PCB, primarily caused by long parallel traces. This interference is due to the distributed capacitance and inductance between the parallel traces. To mitigate crosstalk, the following measures can be implemented:
– Increase the spacing between parallel traces, adhering to the 3W rule.
– Insert a grounded trace between parallel traces.
– Reduce the distance between the signal traces and the ground plane.
7. **Routing Direction Control Rules**
The routing directions of adjacent layers should be orthogonal. Avoid routing different signal lines in the same direction on adjacent layers to minimize inter-layer crosstalk. If this is not possible due to board constraints, especially for high-speed signals, consider using a ground plane to isolate each signal layer, with ground traces separating each signal line. Input and output traces on the PCB should be routed to avoid parallelism, which could lead to feedback. Ideally, a ground trace should be placed between these signals.
8. **Open-Loop Inspection Rules**
It is generally not allowed to leave a trace floating at one end. This is to prevent the “antenna effect” and reduce unwanted electromagnetic radiation and reception, which could result in unpredictable behavior.
9. **Impedance Matching Inspection Rules**
The trace width for a given signal network should remain consistent. Variations in trace width can cause uneven characteristic impedance, leading to signal reflections at high transmission speeds. This situation should be avoided wherever possible. In cases such as connector lead traces or BGA package leads where width changes may be unavoidable, minimize the length of the section with inconsistent impedance.
10. **Closed-Loop Routing Inspection Rules**
Avoid creating signal loops between different layers. Such issues are common in multi-layer PCB designs, and loops can cause radiation interference.
11. **Branch Length Control Rules**
Control the length of trace branches to minimize signal delay. A general guideline is that the delay should be approximately T_delay = Trise/20.
12. **Resonance Control Rules**
This rule applies mainly to high-frequency signal design. The length of a trace should not be an integer multiple of the signal’s wavelength, to avoid resonance effects.
13. **Trace Length Control Rules**
This refers to the “short-line rule.” In PCB design, trace lengths should be kept as short as possible to minimize interference from excessively long traces. This is particularly important for critical signal lines, such as clock traces. These should be placed as far from other components as possible. When driving multiple devices, network topology should be determined based on the specific application requirements.
