As device operating frequencies continue to rise, the signal integrity issues encountered in high-speed PCB designs have become a significant bottleneck for traditional approaches. Engineers face increasing challenges in developing comprehensive solutions. While advanced high-speed simulation and interconnection tools can assist designers in addressing some of these issues, successful high-speed PCB design also necessitates ongoing experience accumulation and in-depth industry collaboration.
**The Influence of Wiring Topology on Signal Integrity**
Signal integrity problems can emerge when signals travel along transmission lines on high-speed PCBs. A netizen named Tongyang from STMicroelectronics raised a question: For a set of buses (address, data, commands) driving up to 4 or 5 devices (such as FLASH, SDRAM, etc.), if the PCB wiring connects to each device sequentially—first to SDRAM, then to FLASH—resulting in a star-shaped distribution from a central point to each device, which method offers better signal integrity?
In this context, some experts indicate that the impact of wiring topology on signal integrity primarily manifests in the inconsistent signal arrival times at each node. Reflected signals also reach certain nodes at varying times, leading to signal quality degradation. Generally, a star topology can promote consistent signal transmission and reflection delays by managing several branches of equal length, thereby enhancing signal quality. However, prior to adopting this topology, one must consider the signal topology nodes, the actual operating principles, and the complexity of wiring. Different buffers can influence signal reflections differently, meaning that a star topology may not adequately address the delays in the data address bus connected to FLASH and SDRAM, thereby failing to guarantee signal quality. Furthermore, high-speed signals typically involve communication between DSP and SDRAM, while FLASH loading rates are generally lower. Consequently, in high-speed simulations, it is essential to ensure the waveform integrity at the node where the actual high-speed signal operates effectively, without needing to focus on the waveform at FLASH. The star topology, compared to daisy chain and other configurations, presents greater wiring challenges, particularly when a substantial number of data address signals are routed in a star configuration.
**The Impact of Pads on High-Speed Signals**
1. In PCB design, a via primarily consists of two components: the central hole and the surrounding pads. An engineer named Fulonm inquired about the influence of pads on high-speed signals. In response, the expert stated that pads do indeed affect high-speed signals, and this impact extends to how similar device packaging influences the devices themselves. A thorough analysis reveals that once a signal exits the IC, it traverses through the bonding wire, pins, package shell, pad, and solder to reach the transmission line. Each joint along this pathway can influence signal quality. However, in practical analysis, providing specific parameters for the pad, solder, and pin is challenging. Therefore, package parameters in the IBIS model are typically utilized to summarize these factors. While such analyses can be applied at lower frequencies, higher frequency signals require more precise simulations, which may not always yield accurate results. Currently, a trend is emerging that utilizes IBIS’s V-I and V-T curves to characterize buffer performance, while SPICE models are employed to describe package parameters.
2. Suppressing electromagnetic interference (EMI) is crucial, as PCBs can be significant sources of EMI. Consequently, PCB design directly impacts the electromagnetic compatibility (EMC) of electronic products. Prioritizing EMC/EMI in high-speed PCB design can significantly reduce the product development cycle and accelerate time to market. This has led many engineers to focus on strategies for mitigating electromagnetic interference in this forum. For instance, during EMC testing, serious harmonics of the clock signal were detected. Should special measures be taken for the power supply pins of the IC utilizing the clock signal? Currently, only decoupling capacitors are connected to these power supply pins. What considerations should be addressed in PCB design to minimize electromagnetic radiation? The expert emphasized that the three key elements of EMC are the radiation source, the transmission pathway, and the victim. The transmission pathway can be categorized into spatial radiation propagation and cable conduction. To suppress harmonics, it is essential first to examine how they propagate. Power supply decoupling addresses the conduction mode of propagation. Additionally, appropriate matching and shielding are necessary.
3. In response to questions from WHITE netizens, the expert highlighted that filtering is an effective strategy for mitigating EMC radiation through conduction. Moreover, one should consider both interference sources and victims. Regarding the interference source, it is advisable to use an oscilloscope to determine whether the signal’s rising edge is excessively fast, or if there are issues such as reflection, overshoot, undershoot, or ringing. If any of these problems are identified, matching can be considered. Furthermore, it is advisable to avoid creating signals with a 50% duty cycle, as these signals lack even sub-harmonics and contain more high-frequency components. For the victims, measures like land coverage may be beneficial.
