In general, the laminated design must adhere to two fundamental principles:

1. Each wiring layer must have an adjacent reference layer (either a power or ground layer);

2. The neighboring main power layer and ground layer should maintain a minimum distance to ensure greater coupling capacitance.

The following outlines the stack configurations from a two-layer board to an eight-layer board for illustrative purposes:

1. Stacking of single-sided PCB and double-sided PCB

For two-layer boards, due to the limited number of layers, lamination issues are not a concern. The control of EMI radiation is primarily addressed through careful wiring and layout considerations.

What are the guidelines for PCB stack design?

The electromagnetic compatibility issues associated with single-layer and double-layer boards are becoming increasingly significant. The primary cause of this trend is the excessive signal loop area, which not only leads to strong electromagnetic radiation but also increases the circuit’s susceptibility to external interference. To enhance the electromagnetic compatibility of the circuit, a straightforward approach is to minimize the loop area of critical signals.

Key signal: From the perspective of electromagnetic compatibility, the term “key signal” refers to signals that produce strong radiation and those that are particularly sensitive to external influences. Typically, signals that generate significant radiation are periodic, such as low-order clock signals or address signals. Conversely, signals that are vulnerable to interference are usually low-level analog signals.


Single and double-layer boards are typically utilized in low-frequency analog designs below 10 KHz:

1) Power traces on the same layer should be routed radially, minimizing the total line length.

2) When routing power and ground wires, they should be placed close together. Position a ground wire adjacent to key signal wires, ensuring it is as close as possible to the signal wire. This configuration minimizes the loop area, thereby reducing the sensitivity of differential mode radiation to external interference. By adding a ground wire next to the signal wire, a loop with the smallest area is created, allowing the signal current to preferentially follow this loop rather than alternate ground paths.

3) For double-layer boards, a ground wire can be laid along the signal wire on the opposite side of the board, directly beneath the signal wire, with the first wire made as wide as feasible. This arrangement results in a loop area equal to the board thickness multiplied by the signal line length.

**Two and Four-Layer Laminates:**

1. SIG-GND(PWR)-PWR(GND)-SIG;

2. GND-SIG(PWR)-SIG(PWR)-GND;

In these two laminated designs, a potential issue arises with the traditional 1.6 mm (62 mil) board thickness. The layer spacing can become excessive, which adversely affects impedance control, interlayer coupling, and shielding. Specifically, the significant distance between power and ground planes reduces board capacitance, hindering noise filtering.

The first scheme is generally applied when there are many chips on the board. This arrangement can achieve better signal integrity (SI) performance, but may not perform as well in terms of electromagnetic interference (EMI). Control is primarily managed through routing and other details. A key consideration is placing the ground layer adjacent to the signal layer with the highest signal density, facilitating the absorption and suppression of radiation; it is advisable to increase board area to adhere to the 20H rule.

The second scheme is typically used when the chip density is low enough and sufficient area is available around the chip for necessary power copper layers. In this configuration, the outer layers of the PCB serve as ground layers, while the two inner layers function as signal/power layers. Routing the power supply on the signal layer with wide lines reduces the path impedance for power supply current, resulting in low impedance for the signal microstrip path. The outer layers can also effectively shield against inner layer signal radiation. This configuration offers optimal EMI control for a four-layer PCB structure.

**Note:** The inner signal and power mixed layers should be separated, with wiring directions oriented perpendicularly to avoid crosstalk. Board area must be appropriately controlled to reflect the 20H rule. To manage impedance, careful arrangement of wiring and copper placement beneath power and ground layers is essential. Additionally, copper on the power or ground layers should be interconnected as much as possible to ensure DC and low-frequency continuity.

**Three and Six-Layer Laminates:**

For designs with higher chip density and clock frequencies, a six-layer board design should be considered, with the following recommended stacking:

1. SIG-GND-SIG-PWR-GND-SIG; This arrangement can provide superior signal integrity, as signal layers are adjacent to ground layers, allowing for better control of trace layer impedance. Both ground layers can effectively absorb magnetic field lines, and an intact power supply and ground layer can provide improved return paths for each signal layer.

2. GND-SIG-GND-PWR-SIG-GND; This scheme is suitable for cases where device density is not excessively high. It retains the advantages of the previous arrangement, with complete ground planes on the top and bottom layers providing better shielding. It is important to keep the power layer close to the layer that is not the primary component surface, as the bottom layer will be more complete, enhancing EMI performance compared to the first option.

**Summary:** For the six-layer board scheme, minimizing the distance between the power and ground layers is crucial for achieving good power and ground coupling. However, with a board thickness of 62 mil and reduced layer spacing, controlling the distance between the main power supply and ground layer can be challenging. Comparing the two schemes, the cost of the second option can significantly increase. Thus, the first option is often preferred for stacking. When designing, it is essential to adhere to the 20H rule and the mirror layer rule.

**Stacking of Four and Eight-Layer Boards:**

1. This stacking method is suboptimal due to poor electromagnetic absorption and high power supply impedance. Its structure is as follows:

1. Signal1 component surface, microstrip wiring layer

2. Signal2 internal microstrip wiring layer, superior routing layer (X direction)

3. Ground

4. Signal3 stripline routing layer, better routing layer (Y direction)

5. Signal4 stripline routing layer

6. Power

7. Signal5 internal microstrip wiring layer

8. Signal6 microstrip trace layer

2. This is a variant of the third stacking method. The addition of the reference layer improves EMI performance, allowing better control of characteristic impedance for each signal layer.

1. Signal1 component surface, microstrip wiring layer, superior routing layer

2. Ground stratum, enhanced electromagnetic wave absorption

3. Signal2 stripline routing layer, good routing layer

4. Power layer, combined with the ground layer below, forms excellent electromagnetic absorption

5. Ground layer

6. Signal3 stripline routing layer, good routing layer

7. Power stratum, exhibiting high power supply impedance

8. Signal4 microstrip wiring layer, superior routing layer

3. This represents the best stacking method, employing multiple ground reference planes for excellent geomagnetic absorption capacity.

1. Signal1 component surface, microstrip wiring layer, superior routing layer

2. Ground stratum, enhanced electromagnetic wave absorption

3. Signal2 stripline routing layer, good routing layer

4. Power layer, combined with the ground layer below, forms excellent electromagnetic absorption

5. Ground layer

6. Signal3 stripline routing layer, good routing layer

7. Ground stratum, enhanced electromagnetic wave absorption

8. Signal4 microstrip wiring layer, superior routing layer

The selection of board layers and stacking methods in PCB design depends on various factors, including the number of signal networks, device density, pin density, signal frequency, and board size. A comprehensive consideration of these factors is essential. For designs with more signal networks, higher device density, greater pin density, and increased signal frequency, multi-layer board designs should be utilized whenever possible. To optimize EMI performance, it is ideal to ensure that each signal layer has its own dedicated reference layer.
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